mirror of
https://github.com/AsahiLinux/u-boot
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e245f1a5db
It also removes the qspi pin configuration done during the board initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
151 lines
4.6 KiB
Text
151 lines
4.6 KiB
Text
/*
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* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
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*
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* Based on:
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* stm32f429.dtsi from Linux
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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u-boot,dm-pre-reloc;
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mac: ethernet@40028000 {
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compatible = "st,stm32-dwmac";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <61>, <62>;
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interrupt-names = "macirq", "eth_wake_irq";
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snps,pbl = <8>;
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snps,mixed-burst;
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dma-ranges;
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status = "disabled";
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};
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qspi: quadspi@A0001000 {
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compatible = "st,stm32-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <92>;
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spi-max-frequency = <108000000>;
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status = "disabled";
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};
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usart1: serial@40011000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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clocks = <&rcc 0 164>;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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rcc: rcc@40023810 {
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#reset-cells = <1>;
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#clock-cells = <2>;
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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clocks = <&clk_hse>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f746-pinctrl";
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ranges = <0 0x40020000 0x3000>;
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u-boot,dm-pre-reloc;
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pins-are-numbered;
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
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bias-disable;
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};
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};
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
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<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
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<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
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<STM32F746_PA2_FUNC_ETH_MDIO>,
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<STM32F746_PC1_FUNC_ETH_MDC>,
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<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
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<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
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<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
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<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
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slew-rate = <2>;
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};
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};
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qspi_pins: qspi@0{
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pins {
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pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
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<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
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<STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
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<STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
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<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
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<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
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slew-rate = <2>;
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};
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};
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};
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};
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};
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&systick {
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status = "okay";
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};
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