mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
fd3a78a538
CS4315 PHY doesn't support phy-reset by software, it needs to reset it by hardware via CPLD control. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
145 lines
2.9 KiB
C
145 lines
2.9 KiB
C
/*
|
|
* Copyright 2009-2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <command.h>
|
|
#include <i2c.h>
|
|
#include <netdev.h>
|
|
#include <linux/compiler.h>
|
|
#include <asm/mmu.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/immap_85xx.h>
|
|
#include <asm/fsl_law.h>
|
|
#include <asm/fsl_serdes.h>
|
|
#include <asm/fsl_portals.h>
|
|
#include <asm/fsl_liodn.h>
|
|
#include <fm_eth.h>
|
|
#include "t208xrdb.h"
|
|
#include "cpld.h"
|
|
#include "../common/vid.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int checkboard(void)
|
|
{
|
|
struct cpu_type *cpu = gd->arch.cpu;
|
|
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
|
|
|
|
printf("Board: %sRDB, ", cpu->name);
|
|
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
|
|
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
|
|
|
|
#ifdef CONFIG_SDCARD
|
|
puts("SD/MMC\n");
|
|
#elif CONFIG_SPIFLASH
|
|
puts("SPI\n");
|
|
#else
|
|
u8 reg;
|
|
|
|
reg = CPLD_READ(flash_csr);
|
|
|
|
if (reg & CPLD_BOOT_SEL) {
|
|
puts("NAND\n");
|
|
} else {
|
|
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
|
|
printf("NOR vBank%d\n", reg);
|
|
}
|
|
#endif
|
|
|
|
puts("SERDES Reference Clocks:\n");
|
|
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
|
|
printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_early_init_r(void)
|
|
{
|
|
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
|
int flash_esel = find_tlb_idx((void *)flashbase, 1);
|
|
/*
|
|
* Remap Boot flash + PROMJET region to caching-inhibited
|
|
* so that flash can be erased properly.
|
|
*/
|
|
|
|
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
|
flush_dcache();
|
|
invalidate_icache();
|
|
if (flash_esel == -1) {
|
|
/* very unlikely unless something is messed up */
|
|
puts("Error: Could not find TLB for FLASH BASE\n");
|
|
flash_esel = 2; /* give our best effort to continue */
|
|
} else {
|
|
/* invalidate existing TLB entry for flash + promjet */
|
|
disable_tlb(flash_esel);
|
|
}
|
|
|
|
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
|
|
|
set_liodns();
|
|
#ifdef CONFIG_SYS_DPAA_QBMAN
|
|
setup_portals();
|
|
#endif
|
|
|
|
/*
|
|
* Adjust core voltage according to voltage ID
|
|
* This function changes I2C mux to channel 2.
|
|
*/
|
|
if (adjust_vdd(0))
|
|
printf("Warning: Adjusting core voltage failed.\n");
|
|
return 0;
|
|
}
|
|
|
|
unsigned long get_board_sys_clk(void)
|
|
{
|
|
return CONFIG_SYS_CLK_FREQ;
|
|
}
|
|
|
|
unsigned long get_board_ddr_clk(void)
|
|
{
|
|
return CONFIG_DDR_CLK_FREQ;
|
|
}
|
|
|
|
int misc_init_r(void)
|
|
{
|
|
u8 reg;
|
|
|
|
/* Reset CS4315 PHY */
|
|
reg = CPLD_READ(reset_ctl);
|
|
reg |= CPLD_RSTCON_EDC_RST;
|
|
CPLD_WRITE(reset_ctl, reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
phys_addr_t base;
|
|
phys_size_t size;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
base = getenv_bootm_low();
|
|
size = getenv_bootm_size();
|
|
|
|
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
|
|
|
#ifdef CONFIG_PCI
|
|
pci_of_setup(blob, bd);
|
|
#endif
|
|
|
|
fdt_fixup_liodn(blob);
|
|
fdt_fixup_dr_usb(blob, bd);
|
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
|
fdt_fixup_fman_ethernet(blob);
|
|
fdt_fixup_board_enet(blob);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|