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7d7bb99e22
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> |
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| .. | ||
| config.h | ||
| cpu.h | ||
| efuse.h | ||
| fw_info.h | ||
| gpio.h | ||
| mbox.h | ||
| soc.h | ||