mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
7cf5597b84
With the move to using binman to generate SPL aka u-boot-spl-ddr.bin and U-Boot proper aka u-boot.itb every board now covers such configuration in its own U-Boot specific device tree include. Move the comon part of that configuration to the common imx8mm-u-boot.dtsi include file. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
114 lines
1.2 KiB
Text
114 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
#include "imx8mm-u-boot.dtsi"
|
|
|
|
/ {
|
|
wdt-reboot {
|
|
compatible = "wdt-reboot";
|
|
wdt = <&wdog1>;
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
};
|
|
|
|
®_usdhc2_vmmc {
|
|
u-boot,off-on-delay-us = <20000>;
|
|
};
|
|
|
|
&pinctrl_reg_usdhc2_vmmc {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&pinctrl_uart2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&pinctrl_usdhc2_gpio {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&pinctrl_usdhc2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&pinctrl_usdhc3 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&gpio1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&gpio2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&gpio3 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&gpio4 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&gpio5 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&uart2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&usdhc1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&usdhc2 {
|
|
u-boot,dm-spl;
|
|
sd-uhs-sdr104;
|
|
sd-uhs-ddr50;
|
|
fsl,signal-voltage-switch-extra-delay-ms = <8>;
|
|
};
|
|
|
|
&usdhc3 {
|
|
u-boot,dm-spl;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
};
|
|
|
|
&i2c1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&pinctrl_i2c1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&pinctrl_pmic {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&fec1 {
|
|
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
&wdog1 {
|
|
u-boot,dm-spl;
|
|
};
|