mirror of
https://github.com/AsahiLinux/u-boot
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2c5f5457bc
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
192 lines
3.8 KiB
C
192 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/syscounter.h>
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#include <asm/armv8/mmu.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <env_internal.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <linux/bitops.h>
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#include <asm/setup.h>
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#include <asm/bootm.h>
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#include <asm/arch-imx/cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 get_cpu_rev(void)
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{
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return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
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}
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#define UNLOCK_WORD 0xD928C520 /* unlock word */
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#define REFRESH_WORD 0xB480A602 /* refresh word */
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static void disable_wdog(void __iomem *wdog_base)
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{
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u32 val_cs = readl(wdog_base + 0x00);
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if (!(val_cs & 0x80))
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return;
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/* default is 32bits cmd */
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writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
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if (!(val_cs & 0x800)) {
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writel(UNLOCK_WORD, (wdog_base + 0x04));
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while (!(readl(wdog_base + 0x00) & 0x800))
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;
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}
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writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
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writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
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writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
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while (!(readl(wdog_base + 0x00) & 0x400))
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;
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}
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void init_wdog(void)
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{
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u32 src_val;
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disable_wdog((void __iomem *)WDG3_BASE_ADDR);
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disable_wdog((void __iomem *)WDG4_BASE_ADDR);
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disable_wdog((void __iomem *)WDG5_BASE_ADDR);
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src_val = readl(0x54460018); /* reset mask */
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src_val &= ~0x1c;
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writel(src_val, 0x54460018);
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}
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static struct mm_region imx93_mem_map[] = {
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{
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/* ROM */
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* OCRAM */
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.virt = 0x20480000UL,
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.phys = 0x20480000UL,
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.size = 0xA0000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* AIPS */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Flexible Serial Peripheral Interface */
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.virt = 0x28000000UL,
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.phys = 0x28000000UL,
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.size = 0x30000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DRAM1 */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = PHYS_SDRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* empty entrie to split table entry 5 if needed when TEEs are used */
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0,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = imx93_mem_map;
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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mac[0] = 0x1;
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mac[1] = 0x2;
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mac[2] = 0x3;
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mac[3] = 0x4;
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mac[4] = 0x5;
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mac[5] = 0x6;
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}
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int print_cpuinfo(void)
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{
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u32 cpurev;
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cpurev = get_cpu_rev();
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printf("CPU: i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
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return 0;
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}
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int arch_misc_init(void)
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{
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return 0;
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}
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int ft_system_setup(void *blob, struct bd_info *bd)
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{
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return 0;
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}
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int arch_cpu_init(void)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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/* Disable wdog */
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init_wdog();
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clock_init();
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}
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return 0;
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}
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int timer_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
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unsigned long freq = readl(&sctr->cntfid0);
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/* Update with accurate clock frequency */
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asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
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clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
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SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
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#endif
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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return 0;
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}
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