mirror of
https://github.com/AsahiLinux/u-boot
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4f01db814a
[ fsl_esdhc commit 52faec3182 ]
Make the code cleaner and drop the old-style #ifdef constructs where it is
possible.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
271 lines
8.3 KiB
C
271 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* FSL SD/MMC Defines
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*-------------------------------------------------------------------
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*
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* Copyright 2019 NXP
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* Yangbo Lu <yangbo.lu@nxp.com>
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*
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* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
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*/
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#ifndef __FSL_ESDHC_IMX_H__
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#define __FSL_ESDHC_IMX_H__
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <asm/byteorder.h>
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/* needed for the mmc_cfg definition */
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#include <mmc.h>
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/* FSL eSDHC-specific constants */
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#define SYSCTL 0x0002e02c
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#define SYSCTL_INITA 0x08000000
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#define SYSCTL_TIMEOUT_MASK 0x000f0000
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#define SYSCTL_CLOCK_MASK 0x0000fff0
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#define SYSCTL_CKEN 0x00000008
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#define SYSCTL_PEREN 0x00000004
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#define SYSCTL_HCKEN 0x00000002
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#define SYSCTL_IPGEN 0x00000001
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#define SYSCTL_RSTA 0x01000000
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#define SYSCTL_RSTC 0x02000000
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#define SYSCTL_RSTD 0x04000000
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#define VENDORSPEC_CKEN 0x00004000
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#define VENDORSPEC_PEREN 0x00002000
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#define VENDORSPEC_HCKEN 0x00001000
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#define VENDORSPEC_IPGEN 0x00000800
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#define VENDORSPEC_INIT 0x20007809
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#define IRQSTAT 0x0002e030
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#define IRQSTAT_DMAE (0x10000000)
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#define IRQSTAT_AC12E (0x01000000)
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#define IRQSTAT_DEBE (0x00400000)
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#define IRQSTAT_DCE (0x00200000)
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#define IRQSTAT_DTOE (0x00100000)
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#define IRQSTAT_CIE (0x00080000)
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#define IRQSTAT_CEBE (0x00040000)
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#define IRQSTAT_CCE (0x00020000)
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#define IRQSTAT_CTOE (0x00010000)
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#define IRQSTAT_CINT (0x00000100)
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#define IRQSTAT_CRM (0x00000080)
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#define IRQSTAT_CINS (0x00000040)
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#define IRQSTAT_BRR (0x00000020)
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#define IRQSTAT_BWR (0x00000010)
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#define IRQSTAT_DINT (0x00000008)
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#define IRQSTAT_BGE (0x00000004)
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#define IRQSTAT_TC (0x00000002)
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#define IRQSTAT_CC (0x00000001)
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#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
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#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
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IRQSTAT_DMAE)
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#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
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#define IRQSTATEN 0x0002e034
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#define IRQSTATEN_DMAE (0x10000000)
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#define IRQSTATEN_AC12E (0x01000000)
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#define IRQSTATEN_DEBE (0x00400000)
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#define IRQSTATEN_DCE (0x00200000)
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#define IRQSTATEN_DTOE (0x00100000)
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#define IRQSTATEN_CIE (0x00080000)
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#define IRQSTATEN_CEBE (0x00040000)
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#define IRQSTATEN_CCE (0x00020000)
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#define IRQSTATEN_CTOE (0x00010000)
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#define IRQSTATEN_CINT (0x00000100)
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#define IRQSTATEN_CRM (0x00000080)
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#define IRQSTATEN_CINS (0x00000040)
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#define IRQSTATEN_BRR (0x00000020)
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#define IRQSTATEN_BWR (0x00000010)
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#define IRQSTATEN_DINT (0x00000008)
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#define IRQSTATEN_BGE (0x00000004)
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#define IRQSTATEN_TC (0x00000002)
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#define IRQSTATEN_CC (0x00000001)
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#define ESDHCCTL 0x0002e40c
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#define ESDHCCTL_PCS (0x00080000)
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#define PRSSTAT 0x0002e024
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#define PRSSTAT_DAT0 (0x01000000)
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#define PRSSTAT_CLSL (0x00800000)
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#define PRSSTAT_WPSPL (0x00080000)
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#define PRSSTAT_CDPL (0x00040000)
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#define PRSSTAT_CINS (0x00010000)
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#define PRSSTAT_BREN (0x00000800)
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#define PRSSTAT_BWEN (0x00000400)
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#define PRSSTAT_SDSTB (0X00000008)
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#define PRSSTAT_DLA (0x00000004)
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#define PRSSTAT_CICHB (0x00000002)
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#define PRSSTAT_CIDHB (0x00000001)
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#define PROCTL 0x0002e028
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#define PROCTL_INIT 0x00000020
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#define PROCTL_DTW_4 0x00000002
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#define PROCTL_DTW_8 0x00000004
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#define PROCTL_D3CD 0x00000008
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#define CMDARG 0x0002e008
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#define XFERTYP 0x0002e00c
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#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
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#define XFERTYP_CMDTYP_NORMAL 0x0
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#define XFERTYP_CMDTYP_SUSPEND 0x00400000
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#define XFERTYP_CMDTYP_RESUME 0x00800000
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#define XFERTYP_CMDTYP_ABORT 0x00c00000
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#define XFERTYP_DPSEL 0x00200000
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#define XFERTYP_CICEN 0x00100000
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#define XFERTYP_CCCEN 0x00080000
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#define XFERTYP_RSPTYP_NONE 0
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#define XFERTYP_RSPTYP_136 0x00010000
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#define XFERTYP_RSPTYP_48 0x00020000
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#define XFERTYP_RSPTYP_48_BUSY 0x00030000
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#define XFERTYP_MSBSEL 0x00000020
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#define XFERTYP_DTDSEL 0x00000010
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#define XFERTYP_DDREN 0x00000008
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#define XFERTYP_AC12EN 0x00000004
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#define XFERTYP_BCEN 0x00000002
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#define XFERTYP_DMAEN 0x00000001
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#define CINS_TIMEOUT 1000
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#define PIO_TIMEOUT 500
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#define DSADDR 0x2e004
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#define CMDRSP0 0x2e010
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#define CMDRSP1 0x2e014
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#define CMDRSP2 0x2e018
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#define CMDRSP3 0x2e01c
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#define DATPORT 0x2e020
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#define WML 0x2e044
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#define WML_WRITE 0x00010000
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#ifdef CONFIG_FSL_SDHC_V2_3
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#define WML_RD_WML_MAX 0x80
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#define WML_WR_WML_MAX 0x80
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#define WML_RD_WML_MAX_VAL 0x0
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#define WML_WR_WML_MAX_VAL 0x0
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#define WML_RD_WML_MASK 0x7f
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#define WML_WR_WML_MASK 0x7f0000
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#else
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#define WML_RD_WML_MAX 0x10
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#define WML_WR_WML_MAX 0x80
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#define WML_RD_WML_MAX_VAL 0x10
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#define WML_WR_WML_MAX_VAL 0x80
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#define WML_RD_WML_MASK 0xff
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#define WML_WR_WML_MASK 0xff0000
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#endif
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#define BLKATTR 0x2e004
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#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
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#define BLKATTR_SIZE(x) (x & 0x1fff)
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#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
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#define HOSTCAPBLT_VS18 0x04000000
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#define HOSTCAPBLT_VS30 0x02000000
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#define HOSTCAPBLT_VS33 0x01000000
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#define HOSTCAPBLT_SRS 0x00800000
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#define HOSTCAPBLT_DMAS 0x00400000
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#define HOSTCAPBLT_HSS 0x00200000
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#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
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/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
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#define MIX_CTRL_DDREN BIT(3)
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#define MIX_CTRL_DTDSEL_READ BIT(4)
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#define MIX_CTRL_AC23EN BIT(7)
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#define MIX_CTRL_EXE_TUNE BIT(22)
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#define MIX_CTRL_SMPCLK_SEL BIT(23)
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#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
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#define MIX_CTRL_FBCLK_SEL BIT(25)
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#define MIX_CTRL_HS400_EN BIT(26)
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#define MIX_CTRL_HS400_ES BIT(27)
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/* Bits 3 and 6 are not SDHCI standard definitions */
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#define MIX_CTRL_SDHCI_MASK 0xb7
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/* Tuning bits */
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#define MIX_CTRL_TUNING_MASK 0x03c00000
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/* strobe dll register */
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#define ESDHC_STROBE_DLL_CTRL 0x70
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#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
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#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
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#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
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#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
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#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
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#define ESDHC_STROBE_DLL_STATUS 0x74
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#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
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#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
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#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
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#define ESDHC_STD_TUNING_EN BIT(24)
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/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
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#define ESDHC_TUNING_START_TAP_MASK 0x7f
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#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE BIT(7)
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#define ESDHC_TUNING_STEP_MASK 0x00070000
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#define ESDHC_TUNING_STEP_SHIFT 16
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#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
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#define ESDHC_FLAG_ENGCM07207 BIT(2)
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#define ESDHC_FLAG_USDHC BIT(3)
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#define ESDHC_FLAG_MAN_TUNING BIT(4)
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#define ESDHC_FLAG_STD_TUNING BIT(5)
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#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
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#define ESDHC_FLAG_ERR004536 BIT(7)
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#define ESDHC_FLAG_HS200 BIT(8)
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#define ESDHC_FLAG_HS400 BIT(9)
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#define ESDHC_FLAG_ERR010450 BIT(10)
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#define ESDHC_FLAG_HS400_ES BIT(11)
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struct fsl_esdhc_cfg {
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phys_addr_t esdhc_base;
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u32 sdhc_clk;
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u8 max_bus_width;
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int wp_enable;
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int vs18_enable; /* Use 1.8V if set to 1 */
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struct mmc_config cfg;
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};
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/* Select the correct accessors depending on endianess */
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#if defined CONFIG_SYS_FSL_ESDHC_LE
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#define esdhc_read32 in_le32
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#define esdhc_write32 out_le32
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#define esdhc_clrsetbits32 clrsetbits_le32
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#define esdhc_clrbits32 clrbits_le32
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#define esdhc_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
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#define esdhc_read32 in_be32
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#define esdhc_write32 out_be32
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#define esdhc_clrsetbits32 clrsetbits_be32
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#define esdhc_clrbits32 clrbits_be32
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#define esdhc_setbits32 setbits_be32
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#elif __BYTE_ORDER == __LITTLE_ENDIAN
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#define esdhc_read32 in_le32
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#define esdhc_write32 out_le32
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#define esdhc_clrsetbits32 clrsetbits_le32
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#define esdhc_clrbits32 clrbits_le32
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#define esdhc_setbits32 setbits_le32
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#elif __BYTE_ORDER == __BIG_ENDIAN
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#define esdhc_read32 in_be32
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#define esdhc_write32 out_be32
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#define esdhc_clrsetbits32 clrsetbits_be32
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#define esdhc_clrbits32 clrbits_be32
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#define esdhc_setbits32 setbits_be32
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#else
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#error "Endianess is not defined: please fix to continue"
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#endif
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#ifdef CONFIG_FSL_ESDHC_IMX
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int fsl_esdhc_mmc_init(struct bd_info *bis);
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int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
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void fdt_fixup_esdhc(void *blob, struct bd_info *bd);
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#else
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static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; }
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static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {}
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#endif /* CONFIG_FSL_ESDHC_IMX */
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void __noreturn mmc_boot(void);
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void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
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#endif /* __FSL_ESDHC_IMX_H__ */
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