mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 16:07:30 +00:00
2c537642e9
A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
407 lines
9 KiB
C
407 lines
9 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include <hwconfig.h>
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#include "../common/qixis.h"
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#include "t102xqds.h"
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#include "t102xqds_qixis.h"
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#include "../common/sleep.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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char buf[64];
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struct cpu_type *cpu = gd->arch.cpu;
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static const char *const freq[] = {"100", "125", "156.25", "100.0"};
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int clock;
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u8 sw = QIXIS_READ(arch);
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printf("Board: %sQDS, ", cpu->name);
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printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
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printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
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#ifdef CONFIG_SDCARD
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puts("SD/MMC\n");
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#elif CONFIG_SPIFLASH
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puts("SPI\n");
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#else
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("PromJet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else if (sw == 0x15)
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printf("IFC Card\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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#endif
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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puts("SERDES Reference: ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 6) & 3;
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printf("Clock1=%sMHz ", freq[clock]);
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clock = (sw >> 4) & 3;
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printf("Clock2=%sMHz\n", freq[clock]);
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return 0;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static int board_mux_lane_to_slot(void)
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{
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s1;
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u8 brdcfg9;
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
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switch (srds_prtcl_s1) {
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case 0:
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/* SerDes1 is not enabled */
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break;
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case 0xd5:
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case 0x5b:
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case 0x6b:
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case 0x77:
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case 0x6f:
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case 0x7f:
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QIXIS_WRITE(brdcfg[12], 0x8c);
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break;
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case 0x40:
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QIXIS_WRITE(brdcfg[12], 0xfc);
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break;
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case 0xd6:
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case 0x5a:
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case 0x6a:
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case 0x56:
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QIXIS_WRITE(brdcfg[12], 0x88);
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break;
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case 0x47:
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QIXIS_WRITE(brdcfg[12], 0xcc);
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break;
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case 0x46:
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QIXIS_WRITE(brdcfg[12], 0xc8);
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break;
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case 0x95:
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case 0x99:
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brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
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QIXIS_WRITE(brdcfg[9], brdcfg9);
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QIXIS_WRITE(brdcfg[12], 0x8c);
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break;
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case 0x116:
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QIXIS_WRITE(brdcfg[12], 0x00);
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break;
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case 0x115:
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case 0x119:
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case 0x129:
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case 0x12b:
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/* Aurora, PCIe, SGMII, SATA */
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QIXIS_WRITE(brdcfg[12], 0x04);
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break;
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default:
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printf("WARNING: unsupported for SerDes Protocol %d\n",
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srds_prtcl_s1);
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return -1;
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}
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return 0;
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}
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#ifdef CONFIG_PPC_T1024
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static void board_mux_setup(void)
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{
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u8 brdcfg15;
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brdcfg15 = QIXIS_READ(brdcfg[15]);
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brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
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if (hwconfig_arg_cmp("pin_mux", "tdm")) {
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/* Route QE_TDM multiplexed signals to TDM Riser slot */
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QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
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QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
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QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
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~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
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} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
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/* to UCC (ProfiBus) interface */
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QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
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} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
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/* to DVI (HDMI) encoder */
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QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
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} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
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/* to DFP (LCD) encoder */
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QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
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BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
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}
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if (hwconfig_arg_cmp("adaptor", "sdxc"))
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/* Route SPI_CS multiplexed signals to SD slot */
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QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
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~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
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}
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#endif
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void board_retimer_ds125df111_init(void)
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{
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u8 reg;
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/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
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reg = I2C_MUX_CH7;
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i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
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reg = I2C_MUX_CH5;
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i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
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/* Access to Control/Shared register */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Read device revision and ID */
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i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast */
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reg = 0x0c;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Reset Channel Registers */
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i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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reg |= 0x4;
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i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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/* Enable override divider select and Enable Override Output Mux */
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i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
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reg |= 0x24;
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i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
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/* Select VCO Divider to full rate (000) */
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i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
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reg &= 0x8f;
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i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
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/* Select active PFD MUX input as re-timed data (001) */
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i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
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reg &= 0x3f;
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reg |= 0x20;
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i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
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/* Set data rate as 10.3125 Gbps */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
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reg = 0xb2;
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i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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reg = 0xcd;
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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}
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int board_early_init_f(void)
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{
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_SYS_FLASH_BASE
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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#endif
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set_liodns();
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#ifdef CONFIG_SYS_DPAA_QBMAN
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setup_portals();
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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board_mux_lane_to_slot();
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board_retimer_ds125df111_init();
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/* Increase IO drive strength to address FCS error on RGMII */
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out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_64:
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return 64000000;
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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#define NUM_SRDS_PLL 2
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int misc_init_r(void)
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{
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#ifdef CONFIG_PPC_T1024
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board_mux_setup();
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#endif
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return 0;
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}
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void fdt_fixup_spi_mux(void *blob)
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{
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int nodeoff = 0;
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if (hwconfig_arg_cmp("pin_mux", "tdm")) {
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"eon,en25s64")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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} else {
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/* remove tdm node */
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"maxim,ds26522")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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fdt_fixup_spi_mux(blob);
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return 0;
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}
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void qixis_dump_switch(void)
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{
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int i, nr_of_cfgsw;
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QIXIS_WRITE(cms[0], 0x00);
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nr_of_cfgsw = QIXIS_READ(cms[1]);
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puts("DIP switch settings dump:\n");
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for (i = 1; i <= nr_of_cfgsw; i++) {
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QIXIS_WRITE(cms[0], i);
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printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
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}
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}
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