u-boot/arch/arm/cpu
Aneesh V 2c451f7831 armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance
	- separate out SOC specific outer cache maintenance from
	  maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
  caches known to ARMv7 CPUs. For instance in Cortex-A8 these
  opertions will affect both L1 and L2 caches. In Cortex-A9
  these will affect only L1 cache

- D-cache operations supported:
	- Invalidate entire D-cache
	- Invalidate D-cache range
	- Flush(clean & invalidate) entire D-cache
	- Flush D-cache range
- I-cache operations supported:
	- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
  used

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
..
arm720t arm: fix incorrect monitor protection region in FLASH 2011-03-27 19:18:52 +02:00
arm920t ARM: drop unsupported 'trab' board 2011-06-22 20:00:51 +02:00
arm925t arm: fix incorrect monitor protection region in FLASH 2011-03-27 19:18:52 +02:00
arm926ejs arm926ejs/at91/lowlevel_init.S: fix defines 2011-06-21 22:26:22 +02:00
arm946es Replace obsolete e-mail address 2011-04-27 19:38:09 +02:00
arm1136 MX31: Make get_reset_cause() static and drop unreachable code 2011-05-23 08:36:46 +02:00
arm1176 SMDK6400: Disable LED function in start.s on the nand booting 2011-03-27 19:19:21 +02:00
arm_intcm arm: fix incorrect monitor protection region in FLASH 2011-03-27 19:18:52 +02:00
armv7 armv7: cache maintenance operations for armv7 2011-07-04 10:55:25 +02:00
ixp Minor coding style fixes. 2011-06-27 22:22:16 +02:00
lh7a40x arm: fix incorrect monitor protection region in FLASH 2011-03-27 19:18:52 +02:00
pxa mv_i2c: use structure to replace the direclty define 2011-04-27 19:38:08 +02:00
s3c44b0 arm: fix incorrect monitor protection region in FLASH 2011-03-27 19:18:52 +02:00
sa1100 arm: fix incorrect monitor protection region in FLASH 2011-03-27 19:18:52 +02:00