mirror of
https://github.com/AsahiLinux/u-boot
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90496afc27
Allows to change clock frequency of debug uart, thus supporting wide range of baudrates. Enable / disable functionality is not implemented yet. In most use cases of SDM845 (i.e. mobile phones and tablets) it's not needed, because qualcomm first stage bootloader leaves it initialized, and on the other hand there's no possibility to replace signed first stage bootloader with u-boot. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm APQ8016, APQ8096
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Based on Little Kernel driver, simplified
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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/* CBCR register fields */
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#define CBCR_BRANCH_ENABLE_BIT BIT(0)
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#define CBCR_BRANCH_OFF_BIT BIT(31)
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extern ulong msm_set_rate(struct clk *clk, ulong rate);
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/* Enable clock controlled by CBC soft macro */
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void clk_enable_cbc(phys_addr_t cbcr)
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{
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setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
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while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
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;
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}
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void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
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{
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if (readl(base + gpll0->status) & gpll0->status_bit)
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return; /* clock already enabled */
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setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
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while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
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;
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}
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#define BRANCH_ON_VAL (0)
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#define BRANCH_NOC_FSM_ON_VAL BIT(29)
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#define BRANCH_CHECK_MASK GENMASK(31, 28)
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void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
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{
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u32 val;
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setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
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do {
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val = readl(base + vclk->cbcr_reg);
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val &= BRANCH_CHECK_MASK;
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} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
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}
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#define APPS_CMD_RCGR_UPDATE BIT(0)
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/* Update clock command via CMD_RCGR */
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void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
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{
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setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
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/* Wait for frequency to be updated. */
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while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)
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;
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}
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#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
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#define CFG_MASK 0x3FFF
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#define CFG_DIVIDER_MASK 0x1F
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/* root set rate for clocks with half integer and MND divider */
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void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
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int div, int m, int n, int source)
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{
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u32 cfg;
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/* M value for MND divider. */
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u32 m_val = m;
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/* NOT(N-M) value for MND divider. */
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u32 n_val = ~((n) - (m)) * !!(n);
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/* NOT 2D value for MND divider. */
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u32 d_val = ~(n);
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/* Program MND values */
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writel(m_val, base + regs->M);
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writel(n_val, base + regs->N);
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writel(d_val, base + regs->D);
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/* setup src select and divider */
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cfg = readl(base + regs->cfg_rcgr);
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cfg &= ~CFG_MASK;
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cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
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/* Set the divider; HW permits fraction dividers (+0.5), but
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for simplicity, we will support integers only */
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if (div)
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cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
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if (n_val)
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cfg |= CFG_MODE_DUAL_EDGE;
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writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
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/* Inform h/w to start using the new config. */
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clk_bcr_update(base + regs->cmd_rcgr);
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}
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static int msm_clk_probe(struct udevice *dev)
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{
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struct msm_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
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{
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return msm_set_rate(clk, rate);
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}
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static struct clk_ops msm_clk_ops = {
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.set_rate = msm_clk_set_rate,
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};
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static const struct udevice_id msm_clk_ids[] = {
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{ .compatible = "qcom,gcc-msm8916" },
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{ .compatible = "qcom,gcc-apq8016" },
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{ .compatible = "qcom,gcc-msm8996" },
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{ .compatible = "qcom,gcc-apq8096" },
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{ .compatible = "qcom,gcc-sdm845" },
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{ }
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};
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U_BOOT_DRIVER(clk_msm) = {
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.name = "clk_msm",
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.id = UCLASS_CLK,
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.of_match = msm_clk_ids,
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.ops = &msm_clk_ops,
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.priv_auto = sizeof(struct msm_clk_priv),
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.probe = msm_clk_probe,
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};
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