mirror of
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e2f95e3a6a
Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
7 lines
209 B
INI
7 lines
209 B
INI
#PBL preamble and RCW header
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aa55aa55 01ee0100
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# serdes protocol
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0608000c 00000000 00000000 00000000
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60000000 00407900 e0106a00 21046000
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00000000 00000000 00000000 00038000
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00000000 001b7200 00000000 00000000
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