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https://github.com/AsahiLinux/u-boot
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678398b19e
In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
183 lines
4.4 KiB
C
183 lines
4.4 KiB
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_AXS101_H_
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#define _CONFIG_AXS101_H_
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/*
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* CPU configuration
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*/
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#define CONFIG_ARC700
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#define CONFIG_ARC_MMU_VER 3
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_CLK_FREQ 750000000
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#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
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/* NAND controller DMA doesn't work correctly with D$ enabled */
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Board configuration
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*/
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
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#define CONFIG_ARCH_EARLY_INIT_R
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#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
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#define ARC_APB_PERIPHERAL_BASE 0xF0000000
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#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
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#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
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/*
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* Memory configuration
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*/
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#define CONFIG_SYS_TEXT_BASE 0x81000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
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#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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/*
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* NAND Flash configuration
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*/
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/*
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* UART configuration
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*
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* CONFIG_CONS_INDEX = 1 - Debug UART
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* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
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*/
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#define CONFIG_CONS_INDEX 4
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#if (CONFIG_CONS_INDEX == 1)
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/* Debug UART */
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# define CONFIG_SYS_NS16550_CLK 33333000
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#else
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/* FPGA UARTs use different clock */
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# define CONFIG_SYS_NS16550_CLK 33333333
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#endif
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#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
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#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
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#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
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#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_BAUDRATE 115200
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/*
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* I2C configuration
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_DW
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#define CONFIG_I2C_ENV_EEPROM_BUS 2
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SPEED1 100000
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#define CONFIG_SYS_I2C_SPEED2 100000
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_SYS_I2C_SLAVE1 0
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#define CONFIG_SYS_I2C_SLAVE2 0
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#define CONFIG_SYS_I2C_BASE 0xE001D000
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#define CONFIG_SYS_I2C_BASE1 0xE001E000
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#define CONFIG_SYS_I2C_BASE2 0xE001F000
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#define CONFIG_SYS_I2C_BUS_MAX 3
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#define IC_CLK 50
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64
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/*
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* SD/MMC configuration
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*/
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DWMMC
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#define CONFIG_DOS_PARTITION
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/*
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* Ethernet PHY configuration
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*/
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#define CONFIG_PHYLIB
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#define CONFIG_MII
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#define CONFIG_PHY_GIGE
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/*
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* Ethernet configuration
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*/
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#define CONFIG_DESIGNWARE_ETH
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#define CONFIG_DW_AUTONEG
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#define CONFIG_NET_MULTI
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/*
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* Command line configuration
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RARP
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#define CONFIG_OF_LIBFDT
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 16
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
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#define CONFIG_ENV_OFFSET 0
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/*
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* Environment configuration
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*/
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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/*
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* Console configuration
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "AXS# "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/*
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* Misc utility configuration
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*/
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#define CONFIG_BOUNCE_BUFFER
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#endif /* _CONFIG_AXS101_H_ */
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