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https://github.com/AsahiLinux/u-boot
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25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
269 lines
7.9 KiB
C
269 lines
7.9 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Configuation settings for the LUBBOCK board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
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#define CONFIG_LCD 1
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#ifdef CONFIG_LCD
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#define CONFIG_SHARP_LM8V31
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#endif
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#define CONFIG_MMC
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#define BOARD_LATE_INIT 1
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_TEXT_BASE 0x0
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_LAN91C96
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#define CONFIG_LAN91C96_BASE 0x0C000000
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/*
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* select serial console configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_FAT
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.21
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#define CONFIG_SERVERIP 192.168.0.250
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#define CONFIG_BOOTCOMMAND "bootm 80000"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_TIMESTAMP
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#ifdef CONFIG_MMC
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#define CONFIG_PXA_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#endif
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000
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#define CONFIG_SYS_DRAM_SIZE 0x04000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
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#define FPGA_REGS_BASE_PHYSICAL 0x08000000
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x00008000
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#define CONFIG_SYS_GPSR1_VAL 0x00FC0382
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#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x00000000
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#define CONFIG_SYS_GPCR2_VAL 0x00000000
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#define CONFIG_SYS_GPDR0_VAL 0x0060A800
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#define CONFIG_SYS_GPDR1_VAL 0x00FF0382
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#define CONFIG_SYS_GPDR2_VAL 0x0001C000
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#define CONFIG_SYS_GAFR0_L_VAL 0x98400000
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#define CONFIG_SYS_GAFR0_U_VAL 0x00002950
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#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
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#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
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#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
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#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
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#define CONFIG_SYS_PSSR_VAL 0x20
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#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
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#define CONFIG_SYS_CKEN 0x0
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x23F223F2
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#define CONFIG_SYS_MSC1_VAL 0x3FF1A441
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#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
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#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
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#define CONFIG_SYS_MDREFR_VAL 0x00018018
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#define CONFIG_SYS_MDMRS_VAL 0x00000000
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000000
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#define CONFIG_SYS_MCMEM0_VAL 0x00010504
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#define CONFIG_SYS_MCMEM1_VAL 0x00010504
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#define CONFIG_SYS_MCATT0_VAL 0x00010504
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#define CONFIG_SYS_MCATT1_VAL 0x00010504
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#define CONFIG_SYS_MCIO0_VAL 0x00004715
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#define CONFIG_SYS_MCIO1_VAL 0x00004715
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#define _LED 0x08000010
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#define LED_BLANK 0x08000040
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/* NOTE: many default partitioning schemes assume the kernel starts at the
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* second sector, not an environment. You have been warned!
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*/
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#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
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#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
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#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
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/*
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* FPGA Offsets
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*/
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#define WHOAMI_OFFSET 0x00
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#define HEXLED_OFFSET 0x10
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#define BLANKLED_OFFSET 0x40
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#define DISCRETELED_OFFSET 0x40
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#define CNFG_SWITCHES_OFFSET 0x50
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#define USER_SWITCHES_OFFSET 0x60
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#define MISC_WR_OFFSET 0x80
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#define MISC_RD_OFFSET 0x90
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#define INT_MASK_OFFSET 0xC0
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#define INT_CLEAR_OFFSET 0xD0
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#define GP_OFFSET 0x100
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#endif /* __CONFIG_H */
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