mirror of
https://github.com/AsahiLinux/u-boot
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9f3183d2d6
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
146 lines
3.7 KiB
C
146 lines
3.7 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#ifdef CONFIG_SYS_FSL_SRDS_1
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static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret = 0;
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#ifdef CONFIG_SYS_FSL_SRDS_1
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ret |= serdes1_prtcl_map[device];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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ret |= serdes2_prtcl_map[device];
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#endif
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return !!ret;
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}
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 cfg = gur_in32(&gur->rcwsr[28]);
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int i;
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switch (sd) {
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#ifdef CONFIG_SYS_FSL_SRDS_1
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case FSL_SRDS_1:
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cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
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cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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case FSL_SRDS_2:
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cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
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cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
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break;
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#endif
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default:
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printf("invalid SerDes%d\n", sd);
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break;
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}
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/* Is serdes enabled at all? */
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if (cfg == 0)
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return -ENODEV;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_get_prtcl(sd, cfg, i) == device)
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return i;
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}
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return -ENODEV;
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}
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void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
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u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 cfg;
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int lane;
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memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
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cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
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cfg >>= sd_prctl_shift;
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printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
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if (!is_serdes_prtcl_valid(sd, cfg))
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printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
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if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
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debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
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else {
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serdes_prtcl_map[lane_prtcl] = 1;
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#ifdef CONFIG_FSL_MC_ENET
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switch (lane_prtcl) {
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case QSGMII_A:
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wriop_init_dpmac(sd, 5, (int)lane_prtcl);
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wriop_init_dpmac(sd, 6, (int)lane_prtcl);
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wriop_init_dpmac(sd, 7, (int)lane_prtcl);
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wriop_init_dpmac(sd, 8, (int)lane_prtcl);
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break;
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case QSGMII_B:
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wriop_init_dpmac(sd, 1, (int)lane_prtcl);
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wriop_init_dpmac(sd, 2, (int)lane_prtcl);
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wriop_init_dpmac(sd, 3, (int)lane_prtcl);
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wriop_init_dpmac(sd, 4, (int)lane_prtcl);
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break;
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case QSGMII_C:
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wriop_init_dpmac(sd, 13, (int)lane_prtcl);
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wriop_init_dpmac(sd, 14, (int)lane_prtcl);
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wriop_init_dpmac(sd, 15, (int)lane_prtcl);
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wriop_init_dpmac(sd, 16, (int)lane_prtcl);
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break;
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case QSGMII_D:
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wriop_init_dpmac(sd, 9, (int)lane_prtcl);
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wriop_init_dpmac(sd, 10, (int)lane_prtcl);
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wriop_init_dpmac(sd, 11, (int)lane_prtcl);
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wriop_init_dpmac(sd, 12, (int)lane_prtcl);
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break;
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default:
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if (lane_prtcl >= SGMII1 &&
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lane_prtcl <= SGMII16)
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wriop_init_dpmac(sd, lane + 1,
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(int)lane_prtcl);
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break;
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}
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#endif
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}
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}
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}
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void fsl_serdes_init(void)
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{
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#ifdef CONFIG_SYS_FSL_SRDS_1
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serdes_init(FSL_SRDS_1,
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CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
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serdes1_prtcl_map);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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serdes_init(FSL_SRDS_2,
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CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
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FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
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FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
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serdes2_prtcl_map);
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#endif
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}
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