mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
0a6b2714ad
A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
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#define __ASM_ARCH_LS102XA_IMMAP_H_
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#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
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#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
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#define IS_E_PROCESSOR(svr) (svr & 0x80000)
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#define IS_SVR_REV(svr, maj, min) \
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((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
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#define SOC_VER_SLS1020 0x00
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#define SOC_VER_LS1020 0x10
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#define SOC_VER_LS1021 0x11
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#define SOC_VER_LS1022 0x12
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#define SOC_MAJOR_VER_1_0 0x1
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#define SOC_MAJOR_VER_2_0 0x2
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#define CCSR_BRR_OFFSET 0xe4
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#define CCSR_SCRATCHRW1_OFFSET 0x200
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#define RCWSR0_SYS_PLL_RAT_SHIFT 25
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#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define RCWSR0_MEM_PLL_RAT_SHIFT 16
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#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define RCWSR4_SRDS1_PRTCL_SHIFT 24
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#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
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#define TIMER_COMP_VAL 0xffffffffffffffffull
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
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#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
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#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
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#define DCFG_DCSR_PORCR1 0
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/*
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* Define default values for some CCSR macros to make header files cleaner
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*
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* To completely disable CCSR relocation in a board header file, define
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* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
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* to a value that is the same as CONFIG_SYS_CCSRBAR.
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*/
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#ifdef CONFIG_SYS_CCSRBAR_PHYS
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#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
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#endif
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#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
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#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
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#endif
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#ifndef CONFIG_SYS_CCSRBAR
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#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
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#endif
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#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
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#endif
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#endif
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#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
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#endif
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#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
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CONFIG_SYS_CCSRBAR_PHYS_LOW)
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struct sys_info {
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unsigned long freq_processor[CONFIG_MAX_CPUS];
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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unsigned long freq_localbus;
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};
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/* Device Configuration and Pin Control */
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struct ccsr_gur {
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u32 porsr1; /* POR status 1 */
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u32 porsr2; /* POR status 2 */
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u8 res_008[0x20-0x8];
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u32 gpporcr1; /* General-purpose POR configuration */
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u32 gpporcr2;
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u32 dcfg_fusesr; /* Fuse status register */
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u8 res_02c[0x70-0x2c];
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u32 devdisr; /* Device disable control */
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u32 devdisr2; /* Device disable control 2 */
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u32 devdisr3; /* Device disable control 3 */
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u32 devdisr4; /* Device disable control 4 */
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u32 devdisr5; /* Device disable control 5 */
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u8 res_084[0x94-0x84];
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u32 coredisru; /* uppper portion for support of 64 cores */
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u32 coredisrl; /* lower portion for support of 64 cores */
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u8 res_09c[0xa4-0x9c];
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u32 svr; /* System version */
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u8 res_0a8[0xb0-0xa8];
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u32 rstcr; /* Reset control */
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u32 rstrqpblsr; /* Reset request preboot loader status */
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u8 res_0b8[0xc0-0xb8];
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u32 rstrqmr1; /* Reset request mask */
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u8 res_0c4[0xc8-0xc4];
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u32 rstrqsr1; /* Reset request status */
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u8 res_0cc[0xd4-0xcc];
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u32 rstrqwdtmrl; /* Reset request WDT mask */
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u8 res_0d8[0xdc-0xd8];
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u32 rstrqwdtsrl; /* Reset request WDT status */
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u8 res_0e0[0xe4-0xe0];
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u32 brrl; /* Boot release */
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u8 res_0e8[0x100-0xe8];
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u32 rcwsr[16]; /* Reset control word status */
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#define RCW_SB_EN_REG_INDEX 7
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#define RCW_SB_EN_MASK 0x00200000
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u8 res_140[0x200-0x140];
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u32 scratchrw[4]; /* Scratch Read/Write */
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u8 res_210[0x300-0x210];
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u32 scratchw1r[4]; /* Scratch Read (Write once) */
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u8 res_310[0x400-0x310];
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u32 crstsr;
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u8 res_404[0x550-0x404];
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u32 sataliodnr;
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u8 res_554[0x604-0x554];
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u32 pamubypenr;
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u32 dmacr1;
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u8 res_60c[0x740-0x60c]; /* add more registers when needed */
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u32 tp_ityp[64]; /* Topology Initiator Type Register */
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struct {
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u32 upper;
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u32 lower;
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} tp_cluster[1]; /* Core Cluster n Topology Register */
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u8 res_848[0xe60-0x848];
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u32 ddrclkdr;
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u8 res_e60[0xe68-0xe64];
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u32 ifcclkdr;
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u8 res_e68[0xe80-0xe6c];
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u32 sdhcpcr;
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};
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#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
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#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
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#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
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#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
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#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
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#define SCFG_PIXCLKCR_PXCKEN 0x80000000
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#define SCFG_QSPI_CLKSEL 0xc0100000
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#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
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#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
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#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
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#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000
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#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000
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#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000
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#define SCFG_ENDIANCR_LE 0x80000000
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/* Supplemental Configuration Unit */
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struct ccsr_scfg {
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u32 dpslpcr;
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u32 resv0[2];
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u32 etsecclkdpslpcr;
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u32 resv1[5];
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u32 fuseovrdcr;
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u32 pixclkcr;
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u32 resv2[5];
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u32 spimsicr;
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u32 resv3[6];
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u32 pex1pmwrcr;
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u32 pex1pmrdsr;
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u32 resv4[3];
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u32 usb3prm1cr;
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u32 usb4prm2cr;
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u32 pex1rdmsgpldlsbsr;
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u32 pex1rdmsgpldmsbsr;
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u32 pex2rdmsgpldlsbsr;
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u32 pex2rdmsgpldmsbsr;
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u32 pex1rdmmsgrqsr;
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u32 pex2rdmmsgrqsr;
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u32 spimsiclrcr;
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u32 pexmscportsr[2];
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u32 pex2pmwrcr;
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u32 resv5[24];
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u32 mac1_streamid;
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u32 mac2_streamid;
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u32 mac3_streamid;
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u32 pex1_streamid;
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u32 pex2_streamid;
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u32 dma_streamid;
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u32 sata_streamid;
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u32 usb3_streamid;
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u32 qe_streamid;
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u32 sdhc_streamid;
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u32 adma_streamid;
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u32 letechsftrstcr;
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u32 core0_sft_rst;
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u32 core1_sft_rst;
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u32 resv6[1];
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u32 usb_hi_addr;
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u32 etsecclkadjcr;
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u32 sai_clk;
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u32 resv7[1];
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u32 dcu_streamid;
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u32 usb2_streamid;
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u32 ftm_reset;
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u32 altcbar;
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u32 qspi_cfg;
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u32 pmcintecr;
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u32 pmcintlecr;
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u32 pmcintsr;
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u32 qos1;
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u32 qos2;
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u32 qos3;
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u32 cci_cfg;
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u32 endiancr;
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u32 etsecdmamcr;
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u32 usb3prm3cr;
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u32 resv9[1];
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u32 debug_streamid;
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u32 resv10[5];
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u32 snpcnfgcr;
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u32 resv11[1];
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u32 intpcr;
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u32 resv12[20];
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u32 scfgrevcr;
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u32 coresrencr;
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u32 pex2pmrdsr;
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u32 eddrtqcfg;
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u32 ddrc2cr;
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u32 ddrc3cr;
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u32 ddrc4cr;
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u32 ddrgcr;
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u32 resv13[120];
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u32 qeioclkcr;
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u32 etsecmcr;
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u32 sdhciovserlcr;
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u32 resv14[61];
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u32 sparecr[8];
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};
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/* Clocking */
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struct ccsr_clk {
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struct {
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u32 clkcncsr; /* core cluster n clock control status */
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u8 res_004[0x1c];
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} clkcsr[2];
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u8 res_040[0x7c0]; /* 0x100 */
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struct {
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u32 pllcngsr;
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u8 res_804[0x1c];
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} pllcgsr[2];
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u8 res_840[0x1c0];
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u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
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u8 res_a04[0x1fc];
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u32 pllpgsr; /* 0xc00 Platform PLL General Status */
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u8 res_c04[0x1c];
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u32 plldgsr; /* 0xc20 DDR PLL General Status */
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u8 res_c24[0x3dc];
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};
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/* System Counter */
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struct sctr_regs {
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u32 cntcr;
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u32 cntsr;
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u32 cntcv1;
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u32 cntcv2;
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u32 resv1[4];
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u32 cntfid0;
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u32 cntfid1;
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u32 resv2[1002];
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u32 counterid[12];
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};
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#define MAX_SERDES 1
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#define SRDS_MAX_LANES 4
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#define SRDS_MAX_BANK 2
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#define SRDS_RSTCTL_RST 0x80000000
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#define SRDS_RSTCTL_RSTDONE 0x40000000
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#define SRDS_RSTCTL_RSTERR 0x20000000
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#define SRDS_RSTCTL_SWRST 0x10000000
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#define SRDS_RSTCTL_SDEN 0x00000020
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#define SRDS_RSTCTL_SDRST_B 0x00000040
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#define SRDS_RSTCTL_PLLRST_B 0x00000080
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#define SRDS_PLLCR0_POFF 0x80000000
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#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
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#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
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#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
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#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
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#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
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#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
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#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
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#define SRDS_PLLCR0_PLL_LCK 0x00800000
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#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
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#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
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#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
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#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
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#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
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#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
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#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
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#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
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struct ccsr_serdes {
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struct {
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u32 rstctl; /* Reset Control Register */
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u32 pllcr0; /* PLL Control Register 0 */
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u32 pllcr1; /* PLL Control Register 1 */
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u32 res_0c; /* 0x00c */
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u32 pllcr3;
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u32 pllcr4;
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u8 res_18[0x20-0x18];
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} bank[2];
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u8 res_40[0x90-0x40];
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u32 srdstcalcr; /* 0x90 TX Calibration Control */
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u8 res_94[0xa0-0x94];
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u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
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u8 res_a4[0xb0-0xa4];
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u32 srdsgr0; /* 0xb0 General Register 0 */
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u8 res_b4[0xe0-0xb4];
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u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
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u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
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u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
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u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
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u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
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u8 res_f4[0x100-0xf4];
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struct {
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u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
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u8 res_104[0x120-0x104];
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} srdslnpssr[4];
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u8 res_180[0x300-0x180];
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u32 srdspexeqcr;
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u32 srdspexeqpcr[11];
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u8 res_330[0x400-0x330];
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u32 srdspexapcr;
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u8 res_404[0x440-0x404];
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u32 srdspexbpcr;
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u8 res_444[0x800-0x444];
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struct {
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u32 gcr0; /* 0x800 General Control Register 0 */
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u32 gcr1; /* 0x804 General Control Register 1 */
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u32 gcr2; /* 0x808 General Control Register 2 */
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u32 sscr0;
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u32 recr0; /* 0x810 Receive Equalization Control */
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u32 recr1;
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u32 tecr0; /* 0x818 Transmit Equalization Control */
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u32 sscr1;
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u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
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u8 res_824[0x83c-0x824];
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u32 tcsr3;
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} lane[4]; /* Lane A, B, C, D, E, F, G, H */
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u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
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};
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#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
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#define CCI400_CTRLORD_EN_BARRIER 0
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#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
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#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
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#define CCI400_SNOOP_REQ_EN 0x00000001
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/* CCI-400 registers */
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struct ccsr_cci400 {
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u32 ctrl_ord; /* Control Override */
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u32 spec_ctrl; /* Speculation Control */
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u32 secure_access; /* Secure Access */
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u32 status; /* Status */
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u32 impr_err; /* Imprecise Error */
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u8 res_14[0x100 - 0x14];
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u32 pmcr; /* Performance Monitor Control */
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u8 res_104[0xfd0 - 0x104];
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u32 pid[8]; /* Peripheral ID */
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u32 cid[4]; /* Component ID */
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struct {
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u32 snoop_ctrl; /* Snoop Control */
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u32 sha_ord; /* Shareable Override */
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u8 res_1008[0x1100 - 0x1008];
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u32 rc_qos_ord; /* read channel QoS Value Override */
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u32 wc_qos_ord; /* read channel QoS Value Override */
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u8 res_1108[0x110c - 0x1108];
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u32 qos_ctrl; /* QoS Control */
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u32 max_ot; /* Max OT */
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u8 res_1114[0x1130 - 0x1114];
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u32 target_lat; /* Target Latency */
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u32 latency_regu; /* Latency Regulation */
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u32 qos_range; /* QoS Range */
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u8 res_113c[0x2000 - 0x113c];
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} slave[5]; /* Slave Interface */
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u8 res_6000[0x9004 - 0x6000];
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u32 cycle_counter; /* Cycle counter */
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u32 count_ctrl; /* Count Control */
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u32 overflow_status; /* Overflow Flag Status */
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u8 res_9010[0xa000 - 0x9010];
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struct {
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u32 event_select; /* Event Select */
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u32 event_count; /* Event Count */
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u32 counter_ctrl; /* Counter Control */
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u32 overflow_status; /* Overflow Flag Status */
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u8 res_a010[0xb000 - 0xa010];
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} pcounter[4]; /* Performance Counter */
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u8 res_e004[0x10000 - 0xe004];
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};
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/* AHCI (sata) register map */
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struct ccsr_ahci {
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u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
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u32 pcfg; /* port config */
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u32 ppcfg; /* port phy1 config */
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u32 pp2c; /* port phy2 config */
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u32 pp3c; /* port phy3 config */
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u32 pp4c; /* port phy4 config */
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u32 pp5c; /* port phy5 config */
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u32 paxic; /* port AXI config */
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u32 axicc; /* AXI cache control */
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u32 axipc; /* AXI PROT control */
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u32 ptc; /* port Trans Config */
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u32 pts; /* port Trans Status */
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u32 plc; /* port link config */
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u32 plc1; /* port link config1 */
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u32 plc2; /* port link config2 */
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u32 pls; /* port link status */
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u32 pls1; /* port link status1 */
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u32 pcmdc; /* port CMD config */
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u32 ppcs; /* port phy control status */
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u32 pberr; /* port 0/1 BIST error */
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u32 cmds; /* port 0/1 CMD status error */
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};
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uint get_svr(void);
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#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
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