u-boot/arch
Stefan Roese 2b181b5b04 arm: mvebu: Flush caches and disable MMU only on A38x
Only with disabled MMU its possible to switch the base register address
on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also
not accessible, as its still locked to cache.

So to fully release / unlock this area from cache, we need to first
flush all caches, then disable the MMU and disable the L2 cache.

On Armada XP this does not seem to be needed. Even worse, with this
code added, I sometimes see strange input charactes loss from the
console.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:48:52 +02:00
..
arc arc: significant cache rework 2015-07-01 17:17:27 +03:00
arm arm: mvebu: Flush caches and disable MMU only on A38x 2015-08-17 18:48:52 +02:00
avr32 avr32: delete ancient board.c 2015-06-10 14:03:26 +02:00
blackfin arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
m68k m68k: cache: add an empty stub functions for invalidate/flush dcache 2015-08-12 20:47:46 -04:00
microblaze arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
mips MIPS: change 'extern inline' to 'static inline' 2015-07-02 11:29:33 +02:00
nds32 arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
nios2 arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
openrisc arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
powerpc Correct License and Copyright information on few files 2015-08-12 20:47:46 -04:00
sandbox dm: test: Add a size to each reg property 2015-07-21 17:39:33 -06:00
sh Move default y configs out of arch/board Kconfig 2015-06-25 22:17:55 -04:00
sparc arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
x86 x86: minnowmax: Define and enable interrupt setup 2015-08-14 09:50:14 -06:00
.gitignore .gitignore: drop include/asm/proc from ignore pattern 2014-06-19 11:18:54 -04:00
Kconfig kbuild: create symbolic link only for ARM, AVR32, SPARC, PowerPC, x86 2015-07-27 15:02:00 -04:00