mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
312c4b1130
Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com
152 lines
4.4 KiB
Text
152 lines
4.4 KiB
Text
menu "FPGA support"
|
|
|
|
config FPGA
|
|
bool
|
|
|
|
config FPGA_ALTERA
|
|
bool "Enable Altera FPGA drivers"
|
|
select FPGA
|
|
help
|
|
Say Y here to enable the Altera FPGA driver
|
|
|
|
This provides basic infrastructure to support Altera FPGA devices.
|
|
Enable Altera FPGA specific functions which includes bitstream
|
|
(in BIT format), fpga and device validation.
|
|
|
|
config FPGA_SOCFPGA
|
|
bool "Enable Gen5 and Arria10 common FPGA drivers"
|
|
select FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Gen5 and Arria10 common FPGA driver
|
|
|
|
This provides common functionality for Gen5 and Arria10 devices.
|
|
|
|
config FPGA_STRATIX_V
|
|
bool "Enable Stratix V FPGA drivers"
|
|
depends on FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Altera Stratix V FPGA specific driver.
|
|
|
|
config FPGA_ACEX1K
|
|
bool "Enable Altera ACEX 1K driver"
|
|
depends on FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Altera ACEX 1K FPGA specific driver.
|
|
|
|
config FPGA_CYCLON2
|
|
bool "Enable Altera FPGA driver for Cyclone II"
|
|
depends on FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Altera Cyclone II FPGA specific driver
|
|
|
|
This provides common functionality for Altera Cyclone II devices.
|
|
Enable FPGA driver for loading bitstream in BIT and BIN format
|
|
on Altera Cyclone II device.
|
|
|
|
config FPGA_INTEL_SDM_MAILBOX
|
|
bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
|
|
depends on TARGET_SOCFPGA_SOC64
|
|
select FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
|
|
|
|
This provides common functionality for Intel FPGA devices.
|
|
Enable FPGA driver for writing full bitstream into Intel FPGA
|
|
devices through SDM (Secure Device Manager) Mailbox.
|
|
|
|
config FPGA_XILINX
|
|
bool "Enable Xilinx FPGA drivers"
|
|
select FPGA
|
|
help
|
|
Enable Xilinx FPGA specific functions which includes bitstream
|
|
(in BIT format), fpga and device validation.
|
|
|
|
config FPGA_ZYNQMPPL
|
|
bool "Enable Xilinx FPGA driver for ZynqMP"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable FPGA driver for loading bitstream in BIT and BIN format
|
|
on Xilinx Zynq UltraScale+ (ZynqMP) device.
|
|
|
|
config FPGA_VERSALPL
|
|
bool "Enable Xilinx FPGA driver for Versal"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable FPGA driver for loading bitstream in PDI format on Xilinx
|
|
Versal device. PDI is a new programmable device image format for
|
|
Versal. The bitstream will only be generated as PDI for Versal
|
|
platform.
|
|
|
|
config FPGA_SPARTAN2
|
|
bool "Enable Spartan2 FPGA driver"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable Spartan2 FPGA driver.
|
|
|
|
config FPGA_SPARTAN3
|
|
bool "Enable Spartan3 FPGA driver"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable Spartan3 FPGA driver for loading in BIT format.
|
|
|
|
config FPGA_VIRTEX2
|
|
bool "Enable Xilinx Virtex-II and later FPGA driver"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable Virtex-II FPGA driver for loading in BIT format. This driver
|
|
also supports many newer Xilinx FPGA families.
|
|
|
|
config FPGA_ZYNQPL
|
|
bool "Enable Xilinx FPGA for Zynq"
|
|
depends on ARCH_ZYNQ
|
|
help
|
|
Enable FPGA driver for loading bitstream in BIT and BIN format
|
|
on Xilinx Zynq devices.
|
|
|
|
config SYS_FPGA_CHECK_CTRLC
|
|
bool "Allow Control-C to interrupt FPGA configuration"
|
|
depends on FPGA
|
|
help
|
|
User can interrupt FPGA configuration by pressing CTRL+C.
|
|
|
|
config SYS_FPGA_PROG_FEEDBACK
|
|
bool "Progress output during FPGA configuration"
|
|
depends on FPGA
|
|
default y if FPGA_VIRTEX2
|
|
help
|
|
Enable printing of hash marks during FPGA configuration.
|
|
|
|
config FPGA_LOAD_SECURE
|
|
bool "Enable loading secure bitstreams"
|
|
depends on FPGA
|
|
help
|
|
Enables the fpga loads() functions that are used to load secure
|
|
(authenticated or encrypted or both) bitstreams on to FPGA.
|
|
|
|
config SPL_FPGA_LOAD_SECURE
|
|
bool "Enable loading secure bitstreams for SPL"
|
|
depends on SPL_FPGA
|
|
help
|
|
Enables the fpga loads() functions that are used to load secure
|
|
(authenticated or encrypted or both) bitstreams on to FPGA.
|
|
|
|
config DM_FPGA
|
|
bool "Enable Driver Model for FPGA drivers"
|
|
depends on DM
|
|
select FPGA
|
|
help
|
|
Enable driver model for Field-Programmable Gate Array (FPGA) devices.
|
|
The devices cover a wide range of applications and are configured at
|
|
runtime by loading a bitstream into the FPGA device.
|
|
Loading a bitstream from any kind of storage is the main task of the
|
|
FPGA drivers.
|
|
For now this uclass has no methods yet.
|
|
|
|
config SANDBOX_FPGA
|
|
bool "Enable sandbox FPGA driver"
|
|
depends on SANDBOX && DM_FPGA
|
|
help
|
|
This is a driver model based FPGA driver for sandbox.
|
|
Currently it is a stub only, as there are no usable uclass methods yet.
|
|
|
|
endmenu
|