mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
2af181b53e
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Note that these registers are present within respective IPs but are not populated in Linux DT nodes (as they are configured via TISCI APIs) and hence are added to -u-boot.dtsi for now. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
217 lines
3 KiB
Text
217 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
|
|
*/
|
|
|
|
#include <dt-bindings/net/ti-dp83867.h>
|
|
|
|
/ {
|
|
chosen {
|
|
stdout-path = "serial2:115200n8";
|
|
tick-timer = &timer1;
|
|
};
|
|
|
|
aliases {
|
|
ethernet0 = &cpsw_port1;
|
|
spi0 = &ospi0;
|
|
spi1 = &ospi1;
|
|
remoteproc0 = &mcu_r5fss0_core0;
|
|
remoteproc1 = &mcu_r5fss0_core1;
|
|
remoteproc2 = &main_r5fss0_core0;
|
|
remoteproc3 = &main_r5fss0_core1;
|
|
remoteproc4 = &main_r5fss1_core0;
|
|
remoteproc5 = &main_r5fss1_core1;
|
|
remoteproc6 = &c66_0;
|
|
remoteproc7 = &c66_1;
|
|
remoteproc8 = &c71_0;
|
|
i2c0 = &wkup_i2c0;
|
|
i2c1 = &mcu_i2c0;
|
|
i2c2 = &mcu_i2c1;
|
|
i2c3 = &main_i2c0;
|
|
};
|
|
};
|
|
|
|
&cbass_main{
|
|
u-boot,dm-spl;
|
|
|
|
main-navss {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&cbass_mcu_wakeup {
|
|
u-boot,dm-spl;
|
|
|
|
timer1: timer@40400000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x40400000 0x0 0x80>;
|
|
ti,timer-alwon;
|
|
clock-frequency = <250000000>;
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
mcu-navss {
|
|
u-boot,dm-spl;
|
|
|
|
ringacc@2b800000 {
|
|
reg = <0x0 0x2b800000 0x0 0x400000>,
|
|
<0x0 0x2b000000 0x0 0x400000>,
|
|
<0x0 0x28590000 0x0 0x100>,
|
|
<0x0 0x2a500000 0x0 0x40000>,
|
|
<0x0 0x28440000 0x0 0x40000>;
|
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
dma-controller@285c0000 {
|
|
reg = <0x0 0x285c0000 0x0 0x100>,
|
|
<0x0 0x284c0000 0x0 0x4000>,
|
|
<0x0 0x2a800000 0x0 0x40000>,
|
|
<0x0 0x284a0000 0x0 0x4000>,
|
|
<0x0 0x2aa00000 0x0 0x40000>,
|
|
<0x0 0x28400000 0x0 0x2000>;
|
|
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
|
|
"tchanrt", "rflow";
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
chipid@43000014 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&secure_proxy_main {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&dmsc {
|
|
u-boot,dm-spl;
|
|
k3_sysreset: sysreset-controller {
|
|
compatible = "ti,sci-sysreset";
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&k3_pds {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&k3_clks {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&k3_reset {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&wkup_pmx0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_pmx0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_uart0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&mcu_uart0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_sdhci0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_sdhci1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_usbss0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&usbss0 {
|
|
u-boot,dm-spl;
|
|
ti,usb2-only;
|
|
};
|
|
|
|
&usb0 {
|
|
dr_mode = "peripheral";
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&mcu_cpsw {
|
|
reg = <0x0 0x46000000 0x0 0x200000>,
|
|
<0x0 0x40f00200 0x0 0x2>;
|
|
reg-names = "cpsw_nuss", "mac_efuse";
|
|
/delete-property/ ranges;
|
|
|
|
cpsw-phy-sel@40f04040 {
|
|
compatible = "ti,am654-cpsw-phy-sel";
|
|
reg= <0x0 0x40f04040 0x0 0x4>;
|
|
reg-names = "gmii-sel";
|
|
};
|
|
};
|
|
|
|
&main_mmc1_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&wkup_i2c0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&wkup_i2c0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_i2c0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_i2c0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&exp2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&mcu_fss0_ospi0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&fss {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&ospi0 {
|
|
u-boot,dm-spl;
|
|
|
|
flash@0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&ospi1 {
|
|
u-boot,dm-spl;
|
|
|
|
flash@0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&mcu_fss0_ospi1_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_r5fss0 {
|
|
ti,cluster-mode = <0>;
|
|
};
|
|
|
|
&main_r5fss1 {
|
|
ti,cluster-mode = <0>;
|
|
};
|