u-boot/arch/arm/dts/cn9130-db.dtsi
Konstantin Porotchkin f29eaadeb5 arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00

316 lines
5.9 KiB
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018-2021 Marvell International Ltd.
*/
#include "cn9130.dtsi" /* include SoC device tree */
#include "cn9130-db-dev-info.dtsi"
/ {
model = "DB-CN-9130";
compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
"marvell,cn9030", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp0_i2c0;
gpio0 = &ap_gpio0;
gpio1 = &cp0_gpio0;
gpio2 = &cp0_gpio1;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
cp0 {
config-space {
i2c@701000 {
/* U36 */
expander0: pca953x@21 {
compatible = "nxp,pca9555";
#gpio-cells = <2>;
reg = <0x21>;
status = "okay";
};
};
sdhci@780000 {
vqmmc-supply = <&cp0_reg_sd_vccq>;
vmmc-supply = <&cp0_reg_sd_vcc>;
};
ap_reg_mmc_vccq: ap_mmc_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "ap_mmc_vccq";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
};
cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "cp0-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <100000>;
regulator-force-boot-off;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
compatible = "regulator-fixed";
regulator-name = "cp0-xhci1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <100000>;
regulator-force-boot-off;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "cp0_sd_vccq";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
};
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
compatible = "regulator-fixed";
regulator-name = "cp0_sd_vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 {
compatible = "regulator-fixed";
regulator-min-microamp = <900000>;
regulator-max-microamp = <900000>;
regulator-force-boot-off;
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
};
cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 {
compatible = "regulator-fixed";
regulator-min-microamp = <900000>;
regulator-max-microamp = <900000>;
regulator-force-boot-off;
gpio = <&expander0 5 GPIO_ACTIVE_HIGH>;
};
};
};
};
&uart0 {
status = "okay";
};
/*
* AP related configuration
*/
&ap_pinctl {
/* MPP Bus:
* SDIO [0-10, 12]
* UART0 [11,19]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 1 1 1 1 1 1 1 1 1 1
1 3 1 0 0 0 0 0 0 3 >;
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&ap_emmc_pins>;
vqmmc-supply = <&ap_reg_mmc_vccq>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
status = "okay";
};
/*
* CP related configuration
*/
&cp0_pinctl {
cp0_nand_pins: cp0-nand-pins {
marvell,pins = <15 16 17 18 19 20 21 22 23 24 25 26 27 >;
marvell,function = <1>;
};
cp0_nand_rb: cp0-nand-rb {
marvell,pins = < 13 >;
marvell,function = <2>;
};
};
/*
* CP0
*/
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
&cp0_i2c1 {
status = "okay";
};
/* CON 28 */
&cp0_sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_sdhci_pins>;
bus-width = <4>;
status = "okay";
};
/* U54 */
&cp0_nand {
pinctrl-names = "default";
pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
status = "disabled";
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>, /* CS0 */
<0 0xffffffff>, /* CS1 */
<0 0xffffffff>, /* CS2 */
<0 0xffffffff>; /* CS3 */
status = "disabled";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor", "spi-flash";
reg = <0x0>;
/* On-board MUX does not allow higher frequencies */
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x200000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xe00000>;
};
};
};
};
&cp0_comphy {
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy3 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
};
};
/* SLM-1521-V2, CON6 */
&cp0_pcie0 {
num-lanes = <4>;
status = "disabled";
};
&cp0_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
/* CON56 */
&cp0_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
/* CON57 */
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* SLM-1521-V2, CON2 */
&cp0_sata0 {
status = "okay";
};
&cp0_utmi0 {
status = "okay";
};
&cp0_utmi1 {
status = "okay";
};
&cp0_usb3_0 {
status = "okay";
vbus-supply = <&cp0_reg_usb3_vbus0>;
current-limiter = <&cp0_reg_usb3_current_lim0>;
vbus-disable-delay = <500>;
};
&cp0_usb3_1 {
status = "okay";
vbus-supply = <&cp0_reg_usb3_vbus1>;
current-limiter = <&cp0_reg_usb3_current_lim1>;
vbus-disable-delay = <500>;
};
&cp0_pcie0 {
status = "okay";
};