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b24f119d67
Hello,
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.
/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
CHANGELOG:
Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.
regards,
Ben
377 lines
8.5 KiB
C
377 lines
8.5 KiB
C
/*
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* (C) Copyright 2006 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003,Motorola Inc.
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* Xianghua Xiao <x.xiao@motorola.com>
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* Adapted for Motorola 85xx chip.
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*
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* (C) Copyright 2003
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* Gleb Natapov <gnatapov@mrv.com>
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* Some bits are taken from linux driver writen by adrian@humboldt.co.uk
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*
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* Hardware I2C driver for MPC107 PCI bridge.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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* 20060601: Dave Liu (daveliu@freescale.com)
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* Unified variable names for mpc83xx
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#ifdef CONFIG_HARD_I2C
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#include <i2c.h>
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#include <asm/i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Three I2C bus speeds are supported here (50kHz, 100kHz
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* and 400kHz). It should be easy to add more. Note that
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* the maximum bus speed for I2C bus 1 is CSB/3, while I2C
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* bus 2 can go as high as CSB.
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* Typical values for CSB are 266MHz and 200MHz. */
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/* 50kH 100kHz 400kHz */
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static const uchar speed_map_266[][3] =
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{{0x2e, 0x2a, 0x20}, /* base 88MHz */
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{0x34, 0x30, 0x28}}; /* base 266 MHz */
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static const uchar speed_map_200[][3] =
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{{0x2c, 0x28, 0x20}, /* base 66 MHz */
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{0x33, 0x2f, 0x26}}; /* base 200 MHz */
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 1. This is necessary because the DDR initialization
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* runs from ROM, and we can't switch buses because we can't modify
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* the i2c_dev variable. Everything gets straightened out once i2c_init
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* is called from RAM. */
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#if defined CFG_SPD_BUS_NUM
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static i2c_t *i2c_dev = CFG_SPD_BUS_NUM;
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#else
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static i2c_t *i2c_dev = I2C_1;
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#endif
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static uchar busNum = I2C_BUS_1 ;
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static int bus_speed[2] = {0, 0};
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static int set_speed(int speed)
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{
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uchar value;
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const uchar *spdPtr;
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/* Global data contains maximum I2C bus 1 speed, which is CSB/3 */
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if(gd->i2c_clk == 88000000)
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{
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spdPtr = speed_map_266[busNum];
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}
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else if(gd->i2c_clk == 66000000)
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{
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spdPtr = speed_map_200[busNum];
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}
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else
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{
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printf("Max I2C bus speed %d not supported\n", gd->i2c_clk);
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return -1;
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}
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switch(speed)
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{
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case 50000:
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value = *(spdPtr + 0);
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break;
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case 100000:
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value = *(spdPtr + 1);
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break;
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case 400000:
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value = *(spdPtr + 2);
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break;
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default:
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printf("I2C bus speed %d not supported\n", speed);
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return -2;
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}
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/* set clock */
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writeb(value, &i2c_dev->fdr);
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bus_speed[busNum] = speed;
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return 0;
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}
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static void _i2c_init(int speed, int slaveadd)
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{
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/* stop I2C controller */
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writeb(0x00 , &i2c_dev->cr);
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/* set clock */
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writeb(speed, &i2c_dev->fdr);
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/* set default filter */
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writeb(0x10,&i2c_dev->dfsrr);
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/* write slave address */
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writeb(slaveadd, &i2c_dev->adr);
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/* clear status register */
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writeb(0x00, &i2c_dev->sr);
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/* start I2C controller */
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writeb(I2C_CR_MEN, &i2c_dev->cr);
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}
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void i2c_init(int speed, int slaveadd)
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{
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/* Set both interfaces to the same speed and slave address */
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/* Note: This function gets called twice - before and after
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* relocation to RAM. The first time it's called, we are unable
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* to change buses, so whichever one 'i2c_dev' was initialized to
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* gets set twice. When run from RAM both buses get set properly */
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i2c_set_bus_num(I2C_BUS_1);
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_i2c_init(speed, slaveadd);
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#ifdef CFG_I2C2_OFFSET
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i2c_set_bus_num(I2C_BUS_2);
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_i2c_init(speed, slaveadd);
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i2c_set_bus_num(I2C_BUS_1);
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#endif /* CFG_I2C2_OFFSET */
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}
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static __inline__ int
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i2c_wait4bus (void)
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{
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ulong timeval = get_timer (0);
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while (readb(&i2c_dev->sr) & I2C_SR_MBB) {
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if (get_timer (timeval) > I2C_TIMEOUT) {
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return -1;
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}
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}
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return 0;
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}
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static __inline__ int
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i2c_wait (int write)
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{
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u32 csr;
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ulong timeval = get_timer(0);
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do {
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csr = readb(&i2c_dev->sr);
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if (!(csr & I2C_SR_MIF))
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continue;
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writeb(0x0, &i2c_dev->sr);
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if (csr & I2C_SR_MAL) {
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debug("i2c_wait: MAL\n");
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return -1;
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}
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if (!(csr & I2C_SR_MCF)) {
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debug("i2c_wait: unfinished\n");
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return -1;
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}
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if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
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debug("i2c_wait: No RXACK\n");
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return -1;
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}
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return 0;
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} while (get_timer (timeval) < I2C_TIMEOUT);
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debug("i2c_wait: timed out\n");
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return -1;
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}
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static __inline__ int
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i2c_write_addr (u8 dev, u8 dir, int rsta)
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{
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
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(rsta?I2C_CR_RSTA:0),
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&i2c_dev->cr);
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writeb((dev << 1) | dir, &i2c_dev->dr);
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if (i2c_wait (I2C_WRITE) < 0)
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return 0;
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return 1;
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}
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static __inline__ int
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__i2c_write (u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
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&i2c_dev->cr);
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for (i=0; i < length; i++) {
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writeb(data[i], &i2c_dev->dr);
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if (i2c_wait (I2C_WRITE) < 0)
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break;
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}
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return i;
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}
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static __inline__ int
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__i2c_read (u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA |
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((length == 1) ? I2C_CR_TXAK : 0),
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&i2c_dev->cr);
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/* dummy read */
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readb(&i2c_dev->dr);
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for (i=0; i < length; i++) {
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if (i2c_wait (I2C_READ) < 0)
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break;
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/* Generate ack on last next to last byte */
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if (i == length - 2)
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writeb(I2C_CR_MEN | I2C_CR_MSTA |
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I2C_CR_TXAK,
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&i2c_dev->cr);
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/* Generate stop on last byte */
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if (i == length - 1)
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writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev->cr);
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data[i] = readb(&i2c_dev->dr);
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}
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return i;
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}
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int
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i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = 0;
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus () < 0)
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goto exit;
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if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
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goto exit;
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if (__i2c_write (&a[4 - alen], alen) != alen)
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goto exit;
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if (i2c_write_addr (dev, I2C_READ, 1) == 0)
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goto exit;
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i = __i2c_read (data, length);
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exit:
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writeb(I2C_CR_MEN, &i2c_dev->cr);
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return !(i == length);
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}
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int
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i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = 0;
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus () < 0)
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goto exit;
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if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
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goto exit;
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if (__i2c_write (&a[4 - alen], alen) != alen)
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goto exit;
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i = __i2c_write (data, length);
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exit:
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writeb(I2C_CR_MEN, &i2c_dev->cr);
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return !(i == length);
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}
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int i2c_probe (uchar chip)
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{
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int tmp;
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/*
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* Try to read the first location of the chip. The underlying
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* driver doesn't appear to support sending just the chip address
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* and looking for an <ACK> back.
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*/
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udelay(10000);
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return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
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}
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uchar i2c_reg_read (uchar i2c_addr, uchar reg)
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{
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uchar buf[1];
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i2c_read (i2c_addr, reg, 1, buf, 1);
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return (buf[0]);
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}
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void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
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{
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i2c_write (i2c_addr, reg, 1, &val, 1);
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}
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int i2c_set_bus_num(uchar bus)
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{
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if(bus == I2C_BUS_1)
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{
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i2c_dev = I2C_1;
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}
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#ifdef CFG_I2C2_OFFSET
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else if(bus == I2C_BUS_2)
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{
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i2c_dev = I2C_2;
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}
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#endif /* CFG_I2C2_OFFSET */
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else
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{
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return -1;
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}
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busNum = bus;
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return 0;
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}
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int i2c_set_bus_speed(int speed)
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{
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return set_speed(speed);
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}
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uchar i2c_get_bus_num(void)
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{
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return busNum;
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}
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int i2c_get_bus_speed(void)
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{
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return bus_speed[busNum];
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}
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#endif /* CONFIG_HARD_I2C */
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