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472d546054
'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
226 lines
5.6 KiB
C
226 lines
5.6 KiB
C
/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/io.h>
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#define OK 0
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#define ERROR (-1)
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extern u_long pci9054_iobase;
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/***************************************************************************
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*
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* Routines for PLX PCI9054 eeprom access
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*
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*/
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static unsigned int PciEepromReadLongVPD (int offs)
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{
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unsigned int value;
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unsigned int ret;
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int count;
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pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
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(offs << 16) | 0x0003);
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count = 0;
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for (;;) {
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udelay (10 * 1000);
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pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
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if ((ret & 0x80000000) != 0) {
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break;
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} else {
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count++;
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if (count > 10) {
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printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
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break;
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}
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}
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}
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pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
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return value;
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}
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static int PciEepromWriteLongVPD (int offs, unsigned int value)
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{
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unsigned int ret;
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int count;
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pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
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pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
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(offs << 16) | 0x80000003);
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count = 0;
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for (;;) {
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udelay (10 * 1000);
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pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
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if ((ret & 0x80000000) == 0) {
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break;
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} else {
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count++;
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if (count > 10) {
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printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
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break;
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}
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}
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}
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return true;
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}
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static void showPci9054 (void)
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{
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int val;
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int l, i;
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/* read 9054-values */
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for (l = 0; l < 6; l++) {
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printf ("%02x: ", l * 0x10);
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for (i = 0; i < 4; i++) {
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pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
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l * 16 + i * 4,
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(unsigned int *)&val);
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printf ("%08x ", val);
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}
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printf ("\n");
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}
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printf ("\n");
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for (l = 0; l < 7; l++) {
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printf ("%02x: ", l * 0x10);
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for (i = 0; i < 4; i++)
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printf ("%08x ",
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PciEepromReadLongVPD ((i + l * 4) * 4));
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printf ("\n");
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}
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printf ("\n");
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}
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static void updatePci9054 (void)
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{
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/*
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* Set EEPROM write-protect register to 0
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*/
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out_be32 ((void *)(pci9054_iobase + 0x0c),
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in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
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/* Long Serial EEPROM Load Registers... */
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PciEepromWriteLongVPD (0x00, 0x905410b5);
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PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
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PciEepromWriteLongVPD (0x08, 0x28140100);
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PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
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PciEepromWriteLongVPD (0x10, 0x00000000);
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/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
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PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
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PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
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PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
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PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
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PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
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PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
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PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
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PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
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PciEepromWriteLongVPD (0x34, 0x00000000);
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PciEepromWriteLongVPD (0x38, 0x00000000);
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PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
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PciEepromWriteLongVPD (0x40, 0x00000000);
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/* Extra Long Serial EEPROM Load Registers... */
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PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
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/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
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/* Offset to LAS1: Group 1: 0x00040000 */
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/* Group 2: 0x00080000 */
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/* Group 3: 0x000c0000 */
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PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
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PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
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PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
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PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
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printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
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}
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static void clearPci9054 (void)
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{
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/*
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* Set EEPROM write-protect register to 0
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*/
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out_be32 ((void *)(pci9054_iobase + 0x0c),
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in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
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/* Long Serial EEPROM Load Registers... */
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PciEepromWriteLongVPD (0x00, 0xffffffff);
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PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
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printf ("Finished clearing PLX PCI9054 EEPROM!\n");
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}
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/* ------------------------------------------------------------------------- */
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int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
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char * const argv[])
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{
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if (strcmp (argv[1], "info") == 0) {
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showPci9054 ();
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return 0;
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}
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if (strcmp (argv[1], "update") == 0) {
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updatePci9054 ();
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return 0;
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}
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if (strcmp (argv[1], "clear") == 0) {
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clearPci9054 ();
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return 0;
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}
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(
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pci9054, 3, 1, do_pci9054,
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"PLX PCI9054 EEPROM access",
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"pci9054 info - print EEPROM values\n"
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"pci9054 update - updates EEPROM with default values"
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);
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/* ------------------------------------------------------------------------- */
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