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Moti Buskila 2ab7bbf71e ddr: marvell: a38x: fix memory cs size function 
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
..
ddr3_debug.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
ddr3_init.c ddr: marvell: a38x: allow board specific ODT configuration 2021-02-26 10:22:29 +01:00
ddr3_init.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_logging_def.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
ddr3_patterns_64bit.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
ddr3_training.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
ddr3_training_bist.c ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_centralization.c ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_db.c ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit 2021-02-26 10:22:29 +01:00
ddr3_training_hw_algo.c mv_ddr: ddr3: Update {min,max}_read_sample calculation 2020-07-09 06:49:44 +02:00
ddr3_training_hw_algo.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ddr3_training_ip.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_ip_bist.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
ddr3_training_ip_centralization.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ddr3_training_ip_db.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
ddr3_training_ip_def.h ddr: marvell: a38x: add 16Gbit memory devices support 2021-02-26 10:22:29 +01:00
ddr3_training_ip_engine.c ddr: marvell: a38x: fix write leveling suplementary algo 2021-02-26 10:22:29 +01:00
ddr3_training_ip_engine.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_ip_flow.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_ip_pbs.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ddr3_training_ip_prv_if.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_leveling.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
ddr3_training_leveling.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr3_training_pbs.c ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
ddr_ml_wrapper.h ARM: mvebu: a38x: Fix comment typo 2020-10-22 11:26:14 -04:00
ddr_topology_def.h ddr: marvell: a38x: import header change from upstream 2021-02-26 10:22:29 +01:00
ddr_training_ip_db.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
dram_if.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
Makefile ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
mv_ddr_build_message.c ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
mv_ddr_common.c ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
mv_ddr_common.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
mv_ddr_plat.c ddr: marvell: a38x: fix memory cs size function 2021-02-26 10:22:29 +01:00
mv_ddr_plat.h ARM: mvebu: restore license information in mv_ddr_plat.{c,h} 2018-12-09 17:10:13 -05:00
mv_ddr_regs.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
mv_ddr_spd.c ddr: marvell: a38x: fix memory size calculation using 32bit bus width 2021-02-26 10:22:29 +01:00
mv_ddr_spd.h ddr: marvell: a38x: fix memory size calculation using 32bit bus width 2021-02-26 10:22:29 +01:00
mv_ddr_sys_env_lib.c ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
mv_ddr_sys_env_lib.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
mv_ddr_topology.c ddr: marvell: a38x: add support for twin-die combined memory device 2021-02-26 10:22:29 +01:00
mv_ddr_topology.h ddr: marvell: a38x: import header change from upstream 2021-02-26 10:22:29 +01:00
mv_ddr_training_db.h ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 2018-12-08 16:19:40 +01:00
seq_exec.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
xor.c ddr: marvell: a38x: fix memory cs size function 2021-02-26 10:22:29 +01:00
xor.h ARM: mvebu: a38x: sync ddr training code with upstream 2018-05-14 10:01:56 +02:00
xor_regs.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00