mirror of
https://github.com/AsahiLinux/u-boot
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2a75bc1303
When programming qspi flash speed we need to check the requested flash speed not to exceed the spi max frequency. In the current implementation we are checking qspi ref clk instead. This commit fixes the issue by checking the requested speed and programs the specified max frequency. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1657893679-20039-5-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
806 lines
20 KiB
C
806 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013 Xilinx, Inc.
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* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
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*
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* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <spi-mem.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
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#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
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#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
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#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
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#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
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#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
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#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
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#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
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#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
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#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
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#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
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#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
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#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
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#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
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#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
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#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
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/* zynq qspi Transmit Data Register */
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#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
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#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
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#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
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#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
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#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
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#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
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#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
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#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
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#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
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#define ZYNQ_QSPI_MAX_BAUD_RATE 0x7
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#define ZYNQ_QSPI_DEFAULT_BAUD_RATE 0x2
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#define ZYNQ_QSPI_FIFO_DEPTH 63
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#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
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/* zynq qspi register set */
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struct zynq_qspi_regs {
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u32 cr; /* 0x00 */
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u32 isr; /* 0x04 */
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u32 ier; /* 0x08 */
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u32 idr; /* 0x0C */
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u32 imr; /* 0x10 */
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u32 enr; /* 0x14 */
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u32 dr; /* 0x18 */
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u32 txd0r; /* 0x1C */
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u32 drxr; /* 0x20 */
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u32 sicr; /* 0x24 */
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u32 txftr; /* 0x28 */
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u32 rxftr; /* 0x2C */
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u32 gpior; /* 0x30 */
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u32 reserved0[19];
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u32 txd1r; /* 0x80 */
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u32 txd2r; /* 0x84 */
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u32 txd3r; /* 0x88 */
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u32 reserved1[5];
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u32 lqspicfg; /* 0xA0 */
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u32 lqspists; /* 0xA4 */
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};
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/* zynq qspi platform data */
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struct zynq_qspi_plat {
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struct zynq_qspi_regs *regs;
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u32 frequency; /* input frequency */
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u32 speed_hz;
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};
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/* zynq qspi priv */
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struct zynq_qspi_priv {
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struct zynq_qspi_regs *regs;
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u8 cs;
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u8 mode;
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u8 fifo_depth;
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u32 freq; /* required frequency */
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u32 max_hz;
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const void *tx_buf;
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void *rx_buf;
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unsigned len;
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int bytes_to_transfer;
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int bytes_to_receive;
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unsigned int is_inst;
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unsigned cs_change:1;
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};
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static int zynq_qspi_of_to_plat(struct udevice *bus)
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{
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struct zynq_qspi_plat *plat = dev_get_plat(bus);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
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node, "reg");
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return 0;
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}
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/**
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* zynq_qspi_init_hw - Initialize the hardware
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* @priv: Pointer to the zynq_qspi_priv structure
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*
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* The default settings of the QSPI controller's configurable parameters on
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* reset are
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* - Master mode
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* - Baud rate divisor is set to 2
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* - Threshold value for TX FIFO not full interrupt is set to 1
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* - Flash memory interface mode enabled
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* - Size of the word to be transferred as 8 bit
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* This function performs the following actions
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* - Disable and clear all the interrupts
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* - Enable manual slave select
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* - Enable auto start
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* - Deselect all the chip select lines
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* - Set the size of the word to be transferred as 32 bit
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* - Set the little endian mode of TX FIFO and
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* - Enable the QSPI controller
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*/
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static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
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{
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struct zynq_qspi_regs *regs = priv->regs;
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u32 confr;
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/* Disable QSPI */
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writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
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/* Disable Interrupts */
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
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/* Clear the TX and RX threshold reg */
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writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
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writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
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/* Clear the RX FIFO */
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while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
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readl(®s->drxr);
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/* Clear Interrupts */
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
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/* Manual slave select and Auto start */
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confr = readl(®s->cr);
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confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
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confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
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ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
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ZYNQ_QSPI_CR_MSTREN_MASK;
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writel(confr, ®s->cr);
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/* Disable the LQSPI feature */
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confr = readl(®s->lqspicfg);
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confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
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writel(confr, ®s->lqspicfg);
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/* Enable SPI */
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writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
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}
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static int zynq_qspi_child_pre_probe(struct udevice *bus)
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{
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struct spi_slave *slave = dev_get_parent_priv(bus);
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struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
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priv->max_hz = slave->max_hz;
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return 0;
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}
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static int zynq_qspi_probe(struct udevice *bus)
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{
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struct zynq_qspi_plat *plat = dev_get_plat(bus);
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struct zynq_qspi_priv *priv = dev_get_priv(bus);
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struct clk clk;
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unsigned long clock;
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int ret;
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priv->regs = plat->regs;
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priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
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ret = clk_get_by_name(bus, "ref_clk", &clk);
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if (ret < 0) {
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dev_err(bus, "failed to get clock\n");
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return ret;
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}
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clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(clock)) {
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dev_err(bus, "failed to get rate\n");
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return clock;
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}
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(bus, "failed to enable clock\n");
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return ret;
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}
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/* init the zynq spi hw */
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zynq_qspi_init_hw(priv);
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plat->frequency = clock;
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plat->speed_hz = plat->frequency / 2;
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debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
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return 0;
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}
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/**
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* zynq_qspi_read_data - Copy data to RX buffer
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* @priv: Pointer to the zynq_qspi_priv structure
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* @data: The 32 bit variable where data is stored
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* @size: Number of bytes to be copied from data to RX buffer
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*/
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static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
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{
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u8 byte3;
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debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
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data, (unsigned)(priv->rx_buf), size);
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if (priv->rx_buf) {
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switch (size) {
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case 1:
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*((u8 *)priv->rx_buf) = data;
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priv->rx_buf += 1;
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break;
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case 2:
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*((u8 *)priv->rx_buf) = data;
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priv->rx_buf += 1;
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*((u8 *)priv->rx_buf) = (u8)(data >> 8);
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priv->rx_buf += 1;
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break;
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case 3:
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*((u8 *)priv->rx_buf) = data;
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priv->rx_buf += 1;
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*((u8 *)priv->rx_buf) = (u8)(data >> 8);
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priv->rx_buf += 1;
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byte3 = (u8)(data >> 16);
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*((u8 *)priv->rx_buf) = byte3;
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priv->rx_buf += 1;
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break;
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case 4:
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/* Can not assume word aligned buffer */
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memcpy(priv->rx_buf, &data, size);
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priv->rx_buf += 4;
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break;
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default:
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/* This will never execute */
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break;
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}
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}
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priv->bytes_to_receive -= size;
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if (priv->bytes_to_receive < 0)
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priv->bytes_to_receive = 0;
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}
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/**
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* zynq_qspi_write_data - Copy data from TX buffer
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* @priv: Pointer to the zynq_qspi_priv structure
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* @data: Pointer to the 32 bit variable where data is to be copied
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* @size: Number of bytes to be copied from TX buffer to data
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*/
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static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
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u32 *data, u8 size)
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{
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if (priv->tx_buf) {
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switch (size) {
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case 1:
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*data = *((u8 *)priv->tx_buf);
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priv->tx_buf += 1;
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*data |= 0xFFFFFF00;
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break;
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case 2:
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*data = *((u8 *)priv->tx_buf);
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priv->tx_buf += 1;
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*data |= (*((u8 *)priv->tx_buf) << 8);
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priv->tx_buf += 1;
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*data |= 0xFFFF0000;
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break;
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case 3:
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*data = *((u8 *)priv->tx_buf);
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priv->tx_buf += 1;
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*data |= (*((u8 *)priv->tx_buf) << 8);
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priv->tx_buf += 1;
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*data |= (*((u8 *)priv->tx_buf) << 16);
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priv->tx_buf += 1;
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*data |= 0xFF000000;
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break;
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case 4:
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/* Can not assume word aligned buffer */
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memcpy(data, priv->tx_buf, size);
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priv->tx_buf += 4;
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break;
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default:
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/* This will never execute */
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break;
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}
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} else {
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*data = 0;
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}
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debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
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*data, (u32)priv->tx_buf, size);
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priv->bytes_to_transfer -= size;
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if (priv->bytes_to_transfer < 0)
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priv->bytes_to_transfer = 0;
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}
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/**
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* zynq_qspi_chipselect - Select or deselect the chip select line
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* @priv: Pointer to the zynq_qspi_priv structure
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* @is_on: Select(1) or deselect (0) the chip select line
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*/
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static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
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{
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u32 confr;
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struct zynq_qspi_regs *regs = priv->regs;
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confr = readl(®s->cr);
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if (is_on) {
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/* Select the slave */
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confr &= ~ZYNQ_QSPI_CR_SS_MASK;
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confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
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ZYNQ_QSPI_CR_SS_MASK;
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} else
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/* Deselect the slave */
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confr |= ZYNQ_QSPI_CR_SS_MASK;
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writel(confr, ®s->cr);
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}
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/**
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* zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
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* @priv: Pointer to the zynq_qspi_priv structure
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* @size: Number of bytes to be copied to fifo
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*/
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static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
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{
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u32 data = 0;
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u32 fifocount = 0;
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unsigned len, offset;
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struct zynq_qspi_regs *regs = priv->regs;
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static const unsigned offsets[4] = {
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ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
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ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
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while ((fifocount < size) &&
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(priv->bytes_to_transfer > 0)) {
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if (priv->bytes_to_transfer >= 4) {
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if (priv->tx_buf) {
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memcpy(&data, priv->tx_buf, 4);
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priv->tx_buf += 4;
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} else {
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data = 0;
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}
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writel(data, ®s->txd0r);
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priv->bytes_to_transfer -= 4;
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fifocount++;
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} else {
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/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
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if (!(readl(®s->isr)
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& ZYNQ_QSPI_IXR_TXOW_MASK) &&
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!priv->rx_buf)
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return;
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len = priv->bytes_to_transfer;
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zynq_qspi_write_data(priv, &data, len);
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offset = (priv->rx_buf) ? offsets[0] : offsets[len];
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writel(data, ®s->cr + (offset / 4));
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}
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}
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}
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/**
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* zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
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* @priv: Pointer to the zynq_qspi structure
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*
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* This function handles TX empty and Mode Fault interrupts only.
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* On TX empty interrupt this function reads the received data from RX FIFO and
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* fills the TX FIFO if there is any data remaining to be transferred.
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* On Mode Fault interrupt this function indicates that transfer is completed,
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* the SPI subsystem will identify the error as the remaining bytes to be
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* transferred is non-zero.
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*
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* returns: 0 for poll timeout
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* 1 transfer operation complete
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*/
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static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
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{
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struct zynq_qspi_regs *regs = priv->regs;
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u32 rxindex = 0;
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u32 rxcount;
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u32 status, timeout;
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/* Poll until any of the interrupt status bits are set */
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timeout = get_timer(0);
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do {
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status = readl(®s->isr);
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} while ((status == 0) &&
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(get_timer(timeout) < ZYNQ_QSPI_WAIT));
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if (status == 0) {
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printf("zynq_qspi_irq_poll: Timeout!\n");
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return -ETIMEDOUT;
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}
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writel(status, ®s->isr);
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/* Disable all interrupts */
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
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if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
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(status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
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/*
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* This bit is set when Tx FIFO has < THRESHOLD entries. We have
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* the THRESHOLD value set to 1, so this bit indicates Tx FIFO
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* is empty
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*/
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rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
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rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
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while ((rxindex < rxcount) &&
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(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
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/* Read out the data from the RX FIFO */
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u32 data;
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data = readl(®s->drxr);
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if (priv->bytes_to_receive >= 4) {
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if (priv->rx_buf) {
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memcpy(priv->rx_buf, &data, 4);
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priv->rx_buf += 4;
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}
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priv->bytes_to_receive -= 4;
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} else {
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zynq_qspi_read_data(priv, data,
|
|
priv->bytes_to_receive);
|
|
}
|
|
rxindex++;
|
|
}
|
|
|
|
if (priv->bytes_to_transfer) {
|
|
/* There is more data to send */
|
|
zynq_qspi_fill_tx_fifo(priv,
|
|
ZYNQ_QSPI_RXFIFO_THRESHOLD);
|
|
|
|
writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
|
|
} else {
|
|
/*
|
|
* If transfer and receive is completed then only send
|
|
* complete signal
|
|
*/
|
|
if (!priv->bytes_to_receive) {
|
|
/* return operation complete */
|
|
writel(ZYNQ_QSPI_IXR_ALL_MASK,
|
|
®s->idr);
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynq_qspi_start_transfer - Initiates the QSPI transfer
|
|
* @priv: Pointer to the zynq_qspi_priv structure
|
|
*
|
|
* This function fills the TX FIFO, starts the QSPI transfer, and waits for the
|
|
* transfer to be completed.
|
|
*
|
|
* returns: Number of bytes transferred in the last transfer
|
|
*/
|
|
static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
|
|
{
|
|
u32 data = 0;
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
|
|
debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
|
|
(u32)priv, (u32)priv, priv->len);
|
|
|
|
priv->bytes_to_transfer = priv->len;
|
|
priv->bytes_to_receive = priv->len;
|
|
|
|
if (priv->len < 4)
|
|
zynq_qspi_fill_tx_fifo(priv, priv->len);
|
|
else
|
|
zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
|
|
|
|
writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
|
|
|
|
/* wait for completion */
|
|
do {
|
|
data = zynq_qspi_irq_poll(priv);
|
|
} while (data == 0);
|
|
|
|
return (priv->len) - (priv->bytes_to_transfer);
|
|
}
|
|
|
|
static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
|
|
{
|
|
unsigned cs_change = 1;
|
|
int status = 0;
|
|
|
|
while (1) {
|
|
/* Select the chip if required */
|
|
if (cs_change)
|
|
zynq_qspi_chipselect(priv, 1);
|
|
|
|
cs_change = priv->cs_change;
|
|
|
|
if (!priv->tx_buf && !priv->rx_buf && priv->len) {
|
|
status = -1;
|
|
break;
|
|
}
|
|
|
|
/* Request the transfer */
|
|
if (priv->len) {
|
|
status = zynq_qspi_start_transfer(priv);
|
|
priv->is_inst = 0;
|
|
}
|
|
|
|
if (status != priv->len) {
|
|
if (status > 0)
|
|
status = -EMSGSIZE;
|
|
debug("zynq_qspi_transfer:%d len:%d\n",
|
|
status, priv->len);
|
|
break;
|
|
}
|
|
status = 0;
|
|
|
|
if (cs_change)
|
|
/* Deselect the chip */
|
|
zynq_qspi_chipselect(priv, 0);
|
|
|
|
break;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static int zynq_qspi_claim_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
|
|
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_release_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
|
|
writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
|
|
|
|
priv->cs = slave_plat->cs;
|
|
priv->tx_buf = dout;
|
|
priv->rx_buf = din;
|
|
priv->len = bitlen / 8;
|
|
|
|
debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
|
|
dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
|
|
|
|
/*
|
|
* Festering sore.
|
|
* Assume that the beginning of a transfer with bits to
|
|
* transmit must contain a device command.
|
|
*/
|
|
if (dout && flags & SPI_XFER_BEGIN)
|
|
priv->is_inst = 1;
|
|
else
|
|
priv->is_inst = 0;
|
|
|
|
if (flags & SPI_XFER_END)
|
|
priv->cs_change = 1;
|
|
else
|
|
priv->cs_change = 0;
|
|
|
|
zynq_qspi_transfer(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct zynq_qspi_plat *plat = dev_get_plat(bus);
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
uint32_t confr;
|
|
u8 baud_rate_val = 0;
|
|
|
|
if (!speed || speed > priv->max_hz)
|
|
speed = priv->max_hz;
|
|
|
|
/* Set the clock frequency */
|
|
confr = readl(®s->cr);
|
|
if (plat->speed_hz != speed) {
|
|
while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
|
|
((plat->frequency /
|
|
(2 << baud_rate_val)) > speed))
|
|
baud_rate_val++;
|
|
|
|
if (baud_rate_val > ZYNQ_QSPI_MAX_BAUD_RATE)
|
|
baud_rate_val = ZYNQ_QSPI_DEFAULT_BAUD_RATE;
|
|
|
|
plat->speed_hz = speed / (2 << baud_rate_val);
|
|
}
|
|
confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
|
|
confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
|
|
|
|
writel(confr, ®s->cr);
|
|
priv->freq = speed;
|
|
|
|
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
uint32_t confr;
|
|
|
|
/* Set the SPI Clock phase and polarities */
|
|
confr = readl(®s->cr);
|
|
confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
|
|
|
|
if (mode & SPI_CPHA)
|
|
confr |= ZYNQ_QSPI_CR_CPHA_MASK;
|
|
if (mode & SPI_CPOL)
|
|
confr |= ZYNQ_QSPI_CR_CPOL_MASK;
|
|
|
|
writel(confr, ®s->cr);
|
|
priv->mode = mode;
|
|
|
|
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_exec_op(struct spi_slave *slave,
|
|
const struct spi_mem_op *op)
|
|
{
|
|
int op_len, pos = 0, ret, i;
|
|
u32 dummy_bytes = 0;
|
|
unsigned int flag = 0;
|
|
const u8 *tx_buf = NULL;
|
|
u8 *rx_buf = NULL;
|
|
|
|
if (op->data.nbytes) {
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
|
rx_buf = op->data.buf.in;
|
|
else
|
|
tx_buf = op->data.buf.out;
|
|
}
|
|
|
|
op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
|
|
if (op->dummy.nbytes) {
|
|
op_len = op->cmd.nbytes + op->addr.nbytes +
|
|
op->dummy.nbytes / op->dummy.buswidth;
|
|
dummy_bytes = op->dummy.nbytes / op->dummy.buswidth;
|
|
}
|
|
|
|
u8 op_buf[op_len];
|
|
|
|
op_buf[pos++] = op->cmd.opcode;
|
|
|
|
if (op->addr.nbytes) {
|
|
for (i = 0; i < op->addr.nbytes; i++)
|
|
op_buf[pos + i] = op->addr.val >>
|
|
(8 * (op->addr.nbytes - i - 1));
|
|
|
|
pos += op->addr.nbytes;
|
|
}
|
|
|
|
if (dummy_bytes)
|
|
memset(op_buf + pos, 0xff, dummy_bytes);
|
|
|
|
/* 1st transfer: opcode + address + dummy cycles */
|
|
/* Make sure to set END bit if no tx or rx data messages follow */
|
|
if (!tx_buf && !rx_buf)
|
|
flag |= SPI_XFER_END;
|
|
|
|
ret = zynq_qspi_xfer(slave->dev, op_len * 8, op_buf, NULL,
|
|
flag | SPI_XFER_BEGIN);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* 2nd transfer: rx or tx data path */
|
|
if (tx_buf || rx_buf) {
|
|
ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf,
|
|
rx_buf, flag | SPI_XFER_END);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
spi_release_bus(slave);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width)
|
|
{
|
|
u32 mode = slave->mode;
|
|
|
|
switch (width) {
|
|
case 1:
|
|
return 0;
|
|
case 2:
|
|
if (mode & SPI_RX_DUAL)
|
|
return 0;
|
|
break;
|
|
case 4:
|
|
if (mode & SPI_RX_QUAD)
|
|
return 0;
|
|
break;
|
|
}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
|
|
const struct spi_mem_op *op)
|
|
{
|
|
if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth))
|
|
return false;
|
|
|
|
if (op->addr.nbytes &&
|
|
zynq_qspi_check_buswidth(slave, op->addr.buswidth))
|
|
return false;
|
|
|
|
if (op->dummy.nbytes &&
|
|
zynq_qspi_check_buswidth(slave, op->dummy.buswidth))
|
|
return false;
|
|
|
|
if (op->data.dir != SPI_MEM_NO_DATA &&
|
|
zynq_qspi_check_buswidth(slave, op->data.buswidth))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
|
|
.exec_op = zynq_qspi_exec_op,
|
|
.supports_op = zynq_qspi_mem_exec_op,
|
|
};
|
|
|
|
static const struct dm_spi_ops zynq_qspi_ops = {
|
|
.claim_bus = zynq_qspi_claim_bus,
|
|
.release_bus = zynq_qspi_release_bus,
|
|
.xfer = zynq_qspi_xfer,
|
|
.set_speed = zynq_qspi_set_speed,
|
|
.set_mode = zynq_qspi_set_mode,
|
|
.mem_ops = &zynq_qspi_mem_ops,
|
|
};
|
|
|
|
static const struct udevice_id zynq_qspi_ids[] = {
|
|
{ .compatible = "xlnx,zynq-qspi-1.0" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(zynq_qspi) = {
|
|
.name = "zynq_qspi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = zynq_qspi_ids,
|
|
.ops = &zynq_qspi_ops,
|
|
.of_to_plat = zynq_qspi_of_to_plat,
|
|
.plat_auto = sizeof(struct zynq_qspi_plat),
|
|
.priv_auto = sizeof(struct zynq_qspi_priv),
|
|
.probe = zynq_qspi_probe,
|
|
.child_pre_probe = zynq_qspi_child_pre_probe,
|
|
};
|