mirror of
https://github.com/AsahiLinux/u-boot
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f81aaa0b33
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
498 lines
10 KiB
C
498 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* spi-synquacer.c - Socionext Synquacer SPI driver
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* Copyright 2021 Linaro Ltd.
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* Copyright 2021 Socionext, Inc.
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <time.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <spi.h>
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#include <wait_bit.h>
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#define MCTRL 0x0
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#define MEN 0
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#define CSEN 1
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#define IPCLK 3
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#define MES 4
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#define SYNCON 5
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#define PCC0 0x4
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#define PCC(n) (PCC0 + (n) * 4)
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#define RTM 3
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#define ACES 2
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#define SAFESYNC 16
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#define CPHA 0
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#define CPOL 1
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#define SSPOL 4
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#define SDIR 7
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#define SS2CD 5
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#define SENDIAN 8
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#define CDRS_SHIFT 9
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#define CDRS_MASK 0x7f
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#define TXF 0x14
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#define TXE 0x18
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#define TXC 0x1c
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#define RXF 0x20
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#define RXE 0x24
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#define RXC 0x28
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#define TFES 1
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#define TFLETE 4
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#define TSSRS 6
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#define RFMTE 5
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#define RSSRS 6
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#define FAULTF 0x2c
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#define FAULTC 0x30
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#define DMCFG 0x34
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#define SSDC 1
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#define MSTARTEN 2
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#define DMSTART 0x38
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#define TRIGGER 0
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#define DMSTOP 8
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#define CS_MASK 3
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#define CS_SHIFT 16
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#define DATA_TXRX 0
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#define DATA_RX 1
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#define DATA_TX 2
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#define DATA_MASK 3
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#define DATA_SHIFT 26
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#define BUS_WIDTH 24
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#define DMBCC 0x3c
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#define DMSTATUS 0x40
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#define RX_DATA_MASK 0x1f
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#define RX_DATA_SHIFT 8
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#define TX_DATA_MASK 0x1f
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#define TX_DATA_SHIFT 16
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#define TXBITCNT 0x44
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#define FIFOCFG 0x4c
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#define BPW_MASK 0x3
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#define BPW_SHIFT 8
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#define RX_FLUSH 11
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#define TX_FLUSH 12
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#define RX_TRSHLD_MASK 0xf
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#define RX_TRSHLD_SHIFT 0
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#define TX_TRSHLD_MASK 0xf
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#define TX_TRSHLD_SHIFT 4
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#define TXFIFO 0x50
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#define RXFIFO 0x90
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#define MID 0xfc
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#define FIFO_DEPTH 16
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#define TX_TRSHLD 4
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#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
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#define TXBIT 1
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#define RXBIT 2
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DECLARE_GLOBAL_DATA_PTR;
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struct synquacer_spi_plat {
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void __iomem *base;
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bool aces, rtm;
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};
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struct synquacer_spi_priv {
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void __iomem *base;
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bool aces, rtm;
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int speed, cs, mode, rwflag;
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void *rx_buf;
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const void *tx_buf;
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unsigned int tx_words, rx_words;
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};
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static void read_fifo(struct synquacer_spi_priv *priv)
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{
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u32 len = readl(priv->base + DMSTATUS);
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u8 *buf = priv->rx_buf;
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int i;
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len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
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len = min_t(unsigned int, len, priv->rx_words);
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for (i = 0; i < len; i++)
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*buf++ = readb(priv->base + RXFIFO);
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priv->rx_buf = buf;
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priv->rx_words -= len;
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}
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static void write_fifo(struct synquacer_spi_priv *priv)
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{
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u32 len = readl(priv->base + DMSTATUS);
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const u8 *buf = priv->tx_buf;
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int i;
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len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
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len = min_t(unsigned int, FIFO_DEPTH - len, priv->tx_words);
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for (i = 0; i < len; i++)
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writeb(*buf++, priv->base + TXFIFO);
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priv->tx_buf = buf;
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priv->tx_words -= len;
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}
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static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active)
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{
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u32 val;
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val = readl(priv->base + DMSTART);
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val &= ~(CS_MASK << CS_SHIFT);
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val |= priv->cs << CS_SHIFT;
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if (active) {
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writel(val, priv->base + DMSTART);
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val = readl(priv->base + DMSTART);
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val &= ~BIT(DMSTOP);
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writel(val, priv->base + DMSTART);
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} else {
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val |= BIT(DMSTOP);
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writel(val, priv->base + DMSTART);
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if (priv->rx_buf) {
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u32 buf[16];
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priv->rx_buf = buf;
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priv->rx_words = 16;
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read_fifo(priv);
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}
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/* wait until slave is deselected */
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while (!(readl(priv->base + TXF) & BIT(TSSRS)) ||
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!(readl(priv->base + RXF) & BIT(RSSRS)))
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;
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}
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}
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static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
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{
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struct udevice *bus = dev->parent;
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struct synquacer_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u32 val, div, bus_width;
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int rwflag;
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rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
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/* if nothing to do */
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if (slave_plat->mode == priv->mode &&
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rwflag == priv->rwflag &&
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slave_plat->cs == priv->cs &&
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slave_plat->max_hz == priv->speed)
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return;
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priv->rwflag = rwflag;
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priv->cs = slave_plat->cs;
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priv->mode = slave_plat->mode;
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priv->speed = slave_plat->max_hz;
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if (priv->mode & SPI_TX_BYTE)
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bus_width = 1;
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else if (priv->mode & SPI_TX_DUAL)
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bus_width = 2;
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else if (priv->mode & SPI_TX_QUAD)
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bus_width = 4;
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else if (priv->mode & SPI_TX_OCTAL)
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bus_width = 8;
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div = DIV_ROUND_UP(125000000, priv->speed);
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val = readl(priv->base + PCC(priv->cs));
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val &= ~BIT(RTM);
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val &= ~BIT(ACES);
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val &= ~BIT(SAFESYNC);
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if ((priv->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3)
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val |= BIT(SAFESYNC);
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if ((priv->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6)
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val |= BIT(SAFESYNC);
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if (priv->mode & SPI_CPHA)
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val |= BIT(CPHA);
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else
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val &= ~BIT(CPHA);
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if (priv->mode & SPI_CPOL)
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val |= BIT(CPOL);
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else
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val &= ~BIT(CPOL);
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if (priv->mode & SPI_CS_HIGH)
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val |= BIT(SSPOL);
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else
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val &= ~BIT(SSPOL);
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if (priv->mode & SPI_LSB_FIRST)
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val |= BIT(SDIR);
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else
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val &= ~BIT(SDIR);
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if (priv->aces)
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val |= BIT(ACES);
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if (priv->rtm)
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val |= BIT(RTM);
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val |= (3 << SS2CD);
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val |= BIT(SENDIAN);
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val &= ~(CDRS_MASK << CDRS_SHIFT);
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val |= ((div >> 1) << CDRS_SHIFT);
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writel(val, priv->base + PCC(priv->cs));
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val = readl(priv->base + FIFOCFG);
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val &= ~(BPW_MASK << BPW_SHIFT);
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val |= (0 << BPW_SHIFT);
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writel(val, priv->base + FIFOCFG);
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val = readl(priv->base + DMSTART);
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val &= ~(DATA_MASK << DATA_SHIFT);
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if (tx && rx)
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val |= (DATA_TXRX << DATA_SHIFT);
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else if (rx)
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val |= (DATA_RX << DATA_SHIFT);
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else
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val |= (DATA_TX << DATA_SHIFT);
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val &= ~(3 << BUS_WIDTH);
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val |= ((bus_width >> 1) << BUS_WIDTH);
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writel(val, priv->base + DMSTART);
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}
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static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *tx_buf, void *rx_buf,
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unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct synquacer_spi_priv *priv = dev_get_priv(bus);
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u32 val, words, busy = 0;
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val = readl(priv->base + FIFOCFG);
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val |= (1 << RX_FLUSH);
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val |= (1 << TX_FLUSH);
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writel(val, priv->base + FIFOCFG);
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synquacer_spi_config(dev, rx_buf, tx_buf);
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priv->tx_buf = tx_buf;
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priv->rx_buf = rx_buf;
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words = bitlen / 8;
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if (tx_buf) {
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busy |= BIT(TXBIT);
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priv->tx_words = words;
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} else {
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busy &= ~BIT(TXBIT);
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priv->tx_words = 0;
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}
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if (rx_buf) {
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busy |= BIT(RXBIT);
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priv->rx_words = words;
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} else {
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busy &= ~BIT(RXBIT);
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priv->rx_words = 0;
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}
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if (flags & SPI_XFER_BEGIN)
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synquacer_cs_set(priv, true);
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if (tx_buf)
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write_fifo(priv);
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if (rx_buf) {
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val = readl(priv->base + FIFOCFG);
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val &= ~(RX_TRSHLD_MASK << RX_TRSHLD_SHIFT);
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val |= ((priv->rx_words > FIFO_DEPTH ?
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RX_TRSHLD : priv->rx_words) << RX_TRSHLD_SHIFT);
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writel(val, priv->base + FIFOCFG);
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}
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writel(~0, priv->base + TXC);
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writel(~0, priv->base + RXC);
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/* Trigger */
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if (flags & SPI_XFER_BEGIN) {
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val = readl(priv->base + DMSTART);
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val |= BIT(TRIGGER);
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writel(val, priv->base + DMSTART);
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}
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while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
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if (priv->rx_words)
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read_fifo(priv);
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else
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busy &= ~BIT(RXBIT);
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if (priv->tx_words) {
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write_fifo(priv);
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} else {
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/* wait for shifter to empty out */
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while (!(readl(priv->base + TXF) & BIT(TFES)))
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cpu_relax();
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busy &= ~BIT(TXBIT);
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}
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}
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if (flags & SPI_XFER_END)
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synquacer_cs_set(priv, false);
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return 0;
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}
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static int synquacer_spi_set_speed(struct udevice *bus, uint speed)
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{
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return 0;
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}
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static int synquacer_spi_set_mode(struct udevice *bus, uint mode)
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{
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return 0;
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}
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static int synquacer_spi_claim_bus(struct udevice *dev)
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{
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return 0;
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}
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static int synquacer_spi_release_bus(struct udevice *dev)
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{
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return 0;
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}
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static void synquacer_spi_disable_module(struct synquacer_spi_priv *priv)
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{
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writel(0, priv->base + MCTRL);
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while (readl(priv->base + MCTRL) & BIT(MES))
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cpu_relax();
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}
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static void synquacer_spi_init(struct synquacer_spi_priv *priv)
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{
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u32 val;
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synquacer_spi_disable_module(priv);
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writel(0, priv->base + TXE);
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writel(0, priv->base + RXE);
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val = readl(priv->base + TXF);
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writel(val, priv->base + TXC);
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val = readl(priv->base + RXF);
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writel(val, priv->base + RXC);
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val = readl(priv->base + FAULTF);
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writel(val, priv->base + FAULTC);
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val = readl(priv->base + DMCFG);
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val &= ~BIT(SSDC);
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val &= ~BIT(MSTARTEN);
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writel(val, priv->base + DMCFG);
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/* Enable module with direct mode */
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val = readl(priv->base + MCTRL);
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val &= ~BIT(IPCLK);
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val &= ~BIT(CSEN);
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val |= BIT(MEN);
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val |= BIT(SYNCON);
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writel(val, priv->base + MCTRL);
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}
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static void synquacer_spi_exit(struct synquacer_spi_priv *priv)
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{
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u32 val;
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synquacer_spi_disable_module(priv);
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/* Enable module with command sequence mode */
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val = readl(priv->base + MCTRL);
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val &= ~BIT(IPCLK);
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val |= BIT(CSEN);
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val |= BIT(MEN);
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val |= BIT(SYNCON);
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writel(val, priv->base + MCTRL);
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while (!(readl(priv->base + MCTRL) & BIT(MES)))
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cpu_relax();
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}
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static int synquacer_spi_probe(struct udevice *bus)
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{
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struct synquacer_spi_plat *plat = dev_get_plat(bus);
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struct synquacer_spi_priv *priv = dev_get_priv(bus);
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priv->base = plat->base;
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priv->aces = plat->aces;
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priv->rtm = plat->rtm;
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synquacer_spi_init(priv);
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return 0;
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}
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static int synquacer_spi_remove(struct udevice *bus)
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{
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struct synquacer_spi_priv *priv = dev_get_priv(bus);
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synquacer_spi_exit(priv);
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return 0;
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}
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static int synquacer_spi_of_to_plat(struct udevice *bus)
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{
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struct synquacer_spi_plat *plat = dev_get_plat(bus);
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struct clk clk;
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plat->base = dev_read_addr_ptr(bus);
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plat->aces = dev_read_bool(bus, "socionext,set-aces");
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plat->rtm = dev_read_bool(bus, "socionext,use-rtm");
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clk_get_by_name(bus, "iHCLK", &clk);
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clk_enable(&clk);
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return 0;
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}
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static const struct dm_spi_ops synquacer_spi_ops = {
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.claim_bus = synquacer_spi_claim_bus,
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.release_bus = synquacer_spi_release_bus,
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.xfer = synquacer_spi_xfer,
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.set_speed = synquacer_spi_set_speed,
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.set_mode = synquacer_spi_set_mode,
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};
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static const struct udevice_id synquacer_spi_ids[] = {
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{ .compatible = "socionext,synquacer-spi" },
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{ /* Sentinel */ }
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};
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U_BOOT_DRIVER(synquacer_spi) = {
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.name = "synquacer_spi",
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.id = UCLASS_SPI,
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.of_match = synquacer_spi_ids,
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.ops = &synquacer_spi_ops,
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.of_to_plat = synquacer_spi_of_to_plat,
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.plat_auto = sizeof(struct synquacer_spi_plat),
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.priv_auto = sizeof(struct synquacer_spi_priv),
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.probe = synquacer_spi_probe,
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.flags = DM_FLAG_OS_PREPARE,
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.remove = synquacer_spi_remove,
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};
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