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8649995c76
The SPI controllers in the Allwinner F1Cx00 series of SoCs are compatible to the H3 IP. The only difference in the integration is the missing mod clock in the F1C100, instead the SPI clock is directly derived from the AHB clock. We *should* be able to model this through the DT, but the addition of get_rate() requires quite some refactoring, so it's not really worth in this simple case: We programmed both the PLL_PERIPH to 600 MHz and the PLL/AHB divider to 3 in the SPL, so we know the SPI base clock is 200 MHz. Since we used a hard coded fixed clock rate of 24 MHz for all the other SoCs so far, we can as well do the same for the F1C100. Define the SPI input clock and maximum frequency differently when compiling for the F1C100 SoC. Also adjust the power-of-2 divider programming, because that uses a "minus one" encoding, compared to the other SoCs. This allows to enable SPI flash support for the F1C100 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
572 lines
13 KiB
C
572 lines
13 KiB
C
/*
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* (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
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* S.J.R. van Schaik <stephan@whiteboxsystems.nl>
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* M.B.W. Wajer <merlijn@whiteboxsystems.nl>
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*
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* (C) Copyright 2017 Olimex Ltd..
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* Stefan Mavrodiev <stefan@olimex.com>
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*
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* Based on linux spi driver. Original copyright follows:
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* linux/drivers/spi/spi-sun4i.c
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*
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* Copyright (C) 2012 - 2014 Allwinner Tech
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* Pan Nan <pannan@allwinnertech.com>
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*
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* Copyright (C) 2014 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <spi.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/global_data.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* sun4i spi registers */
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#define SUN4I_RXDATA_REG 0x00
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#define SUN4I_TXDATA_REG 0x04
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#define SUN4I_CTL_REG 0x08
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#define SUN4I_CLK_CTL_REG 0x1c
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#define SUN4I_BURST_CNT_REG 0x20
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#define SUN4I_XMIT_CNT_REG 0x24
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#define SUN4I_FIFO_STA_REG 0x28
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/* sun6i spi registers */
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_TFR_CTL_REG 0x08
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#define SUN6I_FIFO_CTL_REG 0x18
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#define SUN6I_FIFO_STA_REG 0x1c
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#define SUN6I_CLK_CTL_REG 0x24
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#define SUN6I_BURST_CNT_REG 0x30
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#define SUN6I_XMIT_CNT_REG 0x34
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#define SUN6I_BURST_CTL_REG 0x38
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#define SUN6I_TXDATA_REG 0x200
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#define SUN6I_RXDATA_REG 0x300
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/* sun spi bits */
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#define SUN4I_CTL_ENABLE BIT(0)
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#define SUN4I_CTL_MASTER BIT(1)
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#define SUN4I_CLK_CTL_CDR2_MASK 0xff
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#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
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#define SUN4I_CLK_CTL_CDR1_MASK 0xf
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN4I_CLK_CTL_DRS BIT(12)
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#define SUN4I_MAX_XFER_SIZE 0xffffff
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#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_FIFO_STA_RF_CNT_BITS 0
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#ifdef CONFIG_MACH_SUNIV
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/* the AHB clock, which we programmed to be 1/3 of PLL_PERIPH@600MHz */
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#define SUNXI_INPUT_CLOCK 200000000 /* 200 MHz */
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#define SUN4I_SPI_MAX_RATE (SUNXI_INPUT_CLOCK / 2)
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#else
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/* the SPI mod clock, defaulting to be 1/1 of the HOSC@24MHz */
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#define SUNXI_INPUT_CLOCK 24000000 /* 24 MHz */
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#define SUN4I_SPI_MAX_RATE SUNXI_INPUT_CLOCK
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#endif
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#define SUN4I_SPI_MIN_RATE 3000
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#define SUN4I_SPI_DEFAULT_RATE 1000000
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#define SUN4I_SPI_TIMEOUT_MS 1000
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#define SPI_REG(priv, reg) ((priv)->base + \
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(priv)->variant->regs[reg])
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#define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
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#define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
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SPI_BIT(priv, SPI_TCR_CS_MASK))
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/* sun spi register set */
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enum sun4i_spi_regs {
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SPI_GCR,
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SPI_TCR,
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SPI_FCR,
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SPI_FSR,
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SPI_CCR,
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SPI_BC,
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SPI_TC,
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SPI_BCTL,
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SPI_TXD,
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SPI_RXD,
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};
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/* sun spi register bits */
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enum sun4i_spi_bits {
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SPI_GCR_TP,
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SPI_GCR_SRST,
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SPI_TCR_CPHA,
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SPI_TCR_CPOL,
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SPI_TCR_CS_ACTIVE_LOW,
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SPI_TCR_CS_SEL,
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SPI_TCR_CS_MASK,
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SPI_TCR_XCH,
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SPI_TCR_CS_MANUAL,
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SPI_TCR_CS_LEVEL,
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SPI_FCR_TF_RST,
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SPI_FCR_RF_RST,
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SPI_FSR_RF_CNT_MASK,
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};
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struct sun4i_spi_variant {
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const unsigned long *regs;
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const u32 *bits;
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u32 fifo_depth;
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bool has_soft_reset;
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bool has_burst_ctl;
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};
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struct sun4i_spi_plat {
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struct sun4i_spi_variant *variant;
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u32 base;
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u32 max_hz;
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};
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struct sun4i_spi_priv {
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struct sun4i_spi_variant *variant;
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struct clk clk_ahb, clk_mod;
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struct reset_ctl reset;
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u32 base;
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u32 freq;
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u32 mode;
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const u8 *tx_buf;
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u8 *rx_buf;
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};
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static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
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{
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u8 byte;
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while (len--) {
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byte = readb(SPI_REG(priv, SPI_RXD));
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if (priv->rx_buf)
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*priv->rx_buf++ = byte;
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}
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}
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static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
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{
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u8 byte;
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while (len--) {
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byte = priv->tx_buf ? *priv->tx_buf++ : 0;
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writeb(byte, SPI_REG(priv, SPI_TXD));
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}
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}
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static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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u32 reg;
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reg = readl(SPI_REG(priv, SPI_TCR));
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reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
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reg |= SPI_CS(priv, cs);
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if (enable)
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reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
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else
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reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
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writel(reg, SPI_REG(priv, SPI_TCR));
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}
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static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev);
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int ret;
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if (!enable) {
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clk_disable(&priv->clk_ahb);
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clk_disable(&priv->clk_mod);
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if (reset_valid(&priv->reset))
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reset_assert(&priv->reset);
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return 0;
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}
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ret = clk_enable(&priv->clk_ahb);
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if (ret) {
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dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
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return ret;
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}
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ret = clk_enable(&priv->clk_mod);
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if (ret) {
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dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
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goto err_ahb;
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}
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if (reset_valid(&priv->reset)) {
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ret = reset_deassert(&priv->reset);
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if (ret) {
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dev_err(dev, "failed to deassert reset\n");
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goto err_mod;
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}
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}
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return 0;
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err_mod:
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clk_disable(&priv->clk_mod);
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err_ahb:
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clk_disable(&priv->clk_ahb);
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return ret;
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}
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static void sun4i_spi_set_speed_mode(struct udevice *dev)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev);
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unsigned int div;
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u32 reg;
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/*
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* Setup clock divider.
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*
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* We have two choices there. Either we can use the clock
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* divide rate 1, which is calculated thanks to this formula:
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* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
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* Or we can use CDR2, which is calculated with the formula:
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* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
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* Whether we use the former or the latter is set through the
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* DRS bit.
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*
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* First try CDR2, and if we can't reach the expected
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* frequency, fall back to CDR1.
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*/
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div = DIV_ROUND_UP(SUNXI_INPUT_CLOCK, priv->freq);
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reg = readl(SPI_REG(priv, SPI_CCR));
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if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
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div /= 2;
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if (div > 0)
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div--;
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reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
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reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
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} else {
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div = fls(div - 1);
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/* The F1C100s encodes the divider as 2^(n+1) */
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if (IS_ENABLED(CONFIG_MACH_SUNIV))
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div--;
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reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
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reg |= SUN4I_CLK_CTL_CDR1(div);
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}
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writel(reg, SPI_REG(priv, SPI_CCR));
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reg = readl(SPI_REG(priv, SPI_TCR));
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reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
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if (priv->mode & SPI_CPOL)
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reg |= SPI_BIT(priv, SPI_TCR_CPOL);
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if (priv->mode & SPI_CPHA)
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reg |= SPI_BIT(priv, SPI_TCR_CPHA);
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writel(reg, SPI_REG(priv, SPI_TCR));
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}
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static int sun4i_spi_claim_bus(struct udevice *dev)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
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int ret;
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ret = sun4i_spi_set_clock(dev->parent, true);
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if (ret)
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return ret;
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setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
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SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
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if (priv->variant->has_soft_reset)
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setbits_le32(SPI_REG(priv, SPI_GCR),
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SPI_BIT(priv, SPI_GCR_SRST));
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setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
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SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
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sun4i_spi_set_speed_mode(dev->parent);
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return 0;
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}
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static int sun4i_spi_release_bus(struct udevice *dev)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
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clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
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sun4i_spi_set_clock(dev->parent, false);
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return 0;
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}
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static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u32 len = bitlen / 8;
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u8 nbytes;
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int ret;
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priv->tx_buf = dout;
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priv->rx_buf = din;
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if (bitlen % 8) {
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debug("%s: non byte-aligned SPI transfer.\n", __func__);
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return -ENAVAIL;
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}
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if (flags & SPI_XFER_BEGIN)
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sun4i_spi_set_cs(bus, slave_plat->cs, true);
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/* Reset FIFOs */
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setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
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SPI_BIT(priv, SPI_FCR_TF_RST));
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while (len) {
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/* Setup the transfer now... */
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nbytes = min(len, (priv->variant->fifo_depth - 1));
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/* Setup the counters */
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writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
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writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
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if (priv->variant->has_burst_ctl)
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writel(SUN4I_BURST_CNT(nbytes),
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SPI_REG(priv, SPI_BCTL));
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/* Fill the TX FIFO */
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sun4i_spi_fill_fifo(priv, nbytes);
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/* Start the transfer */
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setbits_le32(SPI_REG(priv, SPI_TCR),
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SPI_BIT(priv, SPI_TCR_XCH));
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/* Wait for the transfer to be done */
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ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR),
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SPI_BIT(priv, SPI_TCR_XCH),
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false, SUN4I_SPI_TIMEOUT_MS, false);
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if (ret < 0) {
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printf("ERROR: sun4i_spi: Timeout transferring data\n");
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sun4i_spi_set_cs(bus, slave_plat->cs, false);
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return ret;
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}
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/* Drain the RX FIFO */
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sun4i_spi_drain_fifo(priv, nbytes);
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len -= nbytes;
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}
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if (flags & SPI_XFER_END)
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sun4i_spi_set_cs(bus, slave_plat->cs, false);
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return 0;
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}
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static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
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{
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struct sun4i_spi_plat *plat = dev_get_plat(dev);
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struct sun4i_spi_priv *priv = dev_get_priv(dev);
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if (speed > plat->max_hz)
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speed = plat->max_hz;
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if (speed < SUN4I_SPI_MIN_RATE)
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speed = SUN4I_SPI_MIN_RATE;
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priv->freq = speed;
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return 0;
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}
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static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev);
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priv->mode = mode;
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return 0;
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}
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static const struct dm_spi_ops sun4i_spi_ops = {
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.claim_bus = sun4i_spi_claim_bus,
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.release_bus = sun4i_spi_release_bus,
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.xfer = sun4i_spi_xfer,
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.set_speed = sun4i_spi_set_speed,
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.set_mode = sun4i_spi_set_mode,
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};
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static int sun4i_spi_probe(struct udevice *bus)
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{
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struct sun4i_spi_plat *plat = dev_get_plat(bus);
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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int ret;
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ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
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if (ret) {
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dev_err(bus, "failed to get ahb clock\n");
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return ret;
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}
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ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
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if (ret) {
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dev_err(bus, "failed to get mod clock\n");
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return ret;
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}
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ret = reset_get_by_index(bus, 0, &priv->reset);
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if (ret && ret != -ENOENT) {
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dev_err(bus, "failed to get reset\n");
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return ret;
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}
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priv->variant = plat->variant;
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priv->base = plat->base;
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priv->freq = plat->max_hz;
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return 0;
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}
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static int sun4i_spi_of_to_plat(struct udevice *bus)
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{
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struct sun4i_spi_plat *plat = dev_get_plat(bus);
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int node = dev_of_offset(bus);
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plat->base = dev_read_addr(bus);
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plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
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plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
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"spi-max-frequency",
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SUN4I_SPI_DEFAULT_RATE);
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if (plat->max_hz > SUN4I_SPI_MAX_RATE)
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plat->max_hz = SUN4I_SPI_MAX_RATE;
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return 0;
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}
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static const unsigned long sun4i_spi_regs[] = {
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[SPI_GCR] = SUN4I_CTL_REG,
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[SPI_TCR] = SUN4I_CTL_REG,
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[SPI_FCR] = SUN4I_CTL_REG,
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[SPI_FSR] = SUN4I_FIFO_STA_REG,
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[SPI_CCR] = SUN4I_CLK_CTL_REG,
|
|
[SPI_BC] = SUN4I_BURST_CNT_REG,
|
|
[SPI_TC] = SUN4I_XMIT_CNT_REG,
|
|
[SPI_TXD] = SUN4I_TXDATA_REG,
|
|
[SPI_RXD] = SUN4I_RXDATA_REG,
|
|
};
|
|
|
|
static const u32 sun4i_spi_bits[] = {
|
|
[SPI_GCR_TP] = BIT(18),
|
|
[SPI_TCR_CPHA] = BIT(2),
|
|
[SPI_TCR_CPOL] = BIT(3),
|
|
[SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
|
|
[SPI_TCR_XCH] = BIT(10),
|
|
[SPI_TCR_CS_SEL] = 12,
|
|
[SPI_TCR_CS_MASK] = 0x3000,
|
|
[SPI_TCR_CS_MANUAL] = BIT(16),
|
|
[SPI_TCR_CS_LEVEL] = BIT(17),
|
|
[SPI_FCR_TF_RST] = BIT(8),
|
|
[SPI_FCR_RF_RST] = BIT(9),
|
|
[SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
|
|
};
|
|
|
|
static const unsigned long sun6i_spi_regs[] = {
|
|
[SPI_GCR] = SUN6I_GBL_CTL_REG,
|
|
[SPI_TCR] = SUN6I_TFR_CTL_REG,
|
|
[SPI_FCR] = SUN6I_FIFO_CTL_REG,
|
|
[SPI_FSR] = SUN6I_FIFO_STA_REG,
|
|
[SPI_CCR] = SUN6I_CLK_CTL_REG,
|
|
[SPI_BC] = SUN6I_BURST_CNT_REG,
|
|
[SPI_TC] = SUN6I_XMIT_CNT_REG,
|
|
[SPI_BCTL] = SUN6I_BURST_CTL_REG,
|
|
[SPI_TXD] = SUN6I_TXDATA_REG,
|
|
[SPI_RXD] = SUN6I_RXDATA_REG,
|
|
};
|
|
|
|
static const u32 sun6i_spi_bits[] = {
|
|
[SPI_GCR_TP] = BIT(7),
|
|
[SPI_GCR_SRST] = BIT(31),
|
|
[SPI_TCR_CPHA] = BIT(0),
|
|
[SPI_TCR_CPOL] = BIT(1),
|
|
[SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
|
|
[SPI_TCR_CS_SEL] = 4,
|
|
[SPI_TCR_CS_MASK] = 0x30,
|
|
[SPI_TCR_CS_MANUAL] = BIT(6),
|
|
[SPI_TCR_CS_LEVEL] = BIT(7),
|
|
[SPI_TCR_XCH] = BIT(31),
|
|
[SPI_FCR_RF_RST] = BIT(15),
|
|
[SPI_FCR_TF_RST] = BIT(31),
|
|
[SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0),
|
|
};
|
|
|
|
static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
|
|
.regs = sun4i_spi_regs,
|
|
.bits = sun4i_spi_bits,
|
|
.fifo_depth = 64,
|
|
};
|
|
|
|
static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
|
|
.regs = sun6i_spi_regs,
|
|
.bits = sun6i_spi_bits,
|
|
.fifo_depth = 128,
|
|
.has_soft_reset = true,
|
|
.has_burst_ctl = true,
|
|
};
|
|
|
|
static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
|
|
.regs = sun6i_spi_regs,
|
|
.bits = sun6i_spi_bits,
|
|
.fifo_depth = 64,
|
|
.has_soft_reset = true,
|
|
.has_burst_ctl = true,
|
|
};
|
|
|
|
static const struct udevice_id sun4i_spi_ids[] = {
|
|
{
|
|
.compatible = "allwinner,sun4i-a10-spi",
|
|
.data = (ulong)&sun4i_a10_spi_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun6i-a31-spi",
|
|
.data = (ulong)&sun6i_a31_spi_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-h3-spi",
|
|
.data = (ulong)&sun8i_h3_spi_variant,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(sun4i_spi) = {
|
|
.name = "sun4i_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = sun4i_spi_ids,
|
|
.ops = &sun4i_spi_ops,
|
|
.of_to_plat = sun4i_spi_of_to_plat,
|
|
.plat_auto = sizeof(struct sun4i_spi_plat),
|
|
.priv_auto = sizeof(struct sun4i_spi_priv),
|
|
.probe = sun4i_spi_probe,
|
|
};
|