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414cc15144
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
496 lines
12 KiB
C
496 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 SPI driver
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*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* NOTE: This driver only supports the SPI-controller chipselects,
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* GPIO driven chipselects are not supported.
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*/
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <cpu_func.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <spi.h>
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#include <asm/cache.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/dma.h>
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#define MXS_SPI_MAX_TIMEOUT 1000000
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#define MXS_SPI_PORT_OFFSET 0x2000
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#define MXS_SSP_CHIPSELECT_MASK 0x00300000
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#define MXS_SSP_CHIPSELECT_SHIFT 20
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#define MXSSSP_SMALL_TRANSFER 512
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/* Base numbers of i.MX2[38] clk for ssp0 IP block */
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#define MXS_SSP_IMX23_CLKID_SSP0 33
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#define MXS_SSP_IMX28_CLKID_SSP0 46
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struct mxs_spi_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_fsl_imx23_spi dtplat;
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#endif
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s32 frequency; /* Default clock frequency, -1 for none */
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fdt_addr_t base; /* SPI IP block base address */
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int num_cs; /* Number of CSes supported */
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int dma_id; /* ID of the DMA channel */
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int clk_id; /* ID of the SSP clock */
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};
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struct mxs_spi_priv {
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struct mxs_ssp_regs *regs;
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unsigned int dma_channel;
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unsigned int max_freq;
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unsigned int clk_id;
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unsigned int mode;
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};
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static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
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{
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writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
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writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
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}
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static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
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{
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writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
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writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
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}
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static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
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char *data, int length, int write,
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unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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if (flags & SPI_XFER_BEGIN)
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mxs_spi_start_xfer(ssp_regs);
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while (length--) {
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/* We transfer 1 byte */
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#if defined(CONFIG_MX23)
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writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
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writel(1, &ssp_regs->hw_ssp_ctrl0_set);
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#elif defined(CONFIG_MX28)
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writel(1, &ssp_regs->hw_ssp_xfer_size);
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#endif
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if ((flags & SPI_XFER_END) && !length)
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mxs_spi_end_xfer(ssp_regs);
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if (write)
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
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else
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
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writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
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if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
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SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for start\n");
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return -ETIMEDOUT;
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}
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if (write)
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writel(*data++, &ssp_regs->hw_ssp_data);
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writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
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if (!write) {
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if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
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SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for data\n");
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return -ETIMEDOUT;
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}
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*data = readl(&ssp_regs->hw_ssp_data);
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data++;
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}
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if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
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SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for finish\n");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
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char *data, int length, int write,
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unsigned long flags)
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{ struct mxs_ssp_regs *ssp_regs = priv->regs;
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const int xfer_max_sz = 0xff00;
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const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
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struct mxs_dma_desc *dp;
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uint32_t ctrl0;
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uint32_t cache_data_count;
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const uint32_t dstart = (uint32_t)data;
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int dmach;
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int tl;
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int ret = 0;
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#if defined(CONFIG_MX23)
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const int mxs_spi_pio_words = 1;
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#elif defined(CONFIG_MX28)
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const int mxs_spi_pio_words = 4;
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#endif
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ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
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memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
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ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
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ctrl0 |= SSP_CTRL0_DATA_XFER;
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if (flags & SPI_XFER_BEGIN)
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ctrl0 |= SSP_CTRL0_LOCK_CS;
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if (!write)
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ctrl0 |= SSP_CTRL0_READ;
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if (length % ARCH_DMA_MINALIGN)
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cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
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else
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cache_data_count = length;
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/* Flush data to DRAM so DMA can pick them up */
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if (write)
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flush_dcache_range(dstart, dstart + cache_data_count);
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/* Invalidate the area, so no writeback into the RAM races with DMA */
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invalidate_dcache_range(dstart, dstart + cache_data_count);
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dmach = priv->dma_channel;
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dp = desc;
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while (length) {
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dp->address = (dma_addr_t)dp;
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dp->cmd.address = (dma_addr_t)data;
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/*
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* This is correct, even though it does indeed look insane.
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* I hereby have to, wholeheartedly, thank Freescale Inc.,
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* for always inventing insane hardware and keeping me busy
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* and employed ;-)
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*/
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if (write)
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dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
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else
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dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
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/*
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* The DMA controller can transfer large chunks (64kB) at
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* time by setting the transfer length to 0. Setting tl to
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* 0x10000 will overflow below and make .data contain 0.
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* Otherwise, 0xff00 is the transfer maximum.
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*/
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if (length >= 0x10000)
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tl = 0x10000;
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else
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tl = min(length, xfer_max_sz);
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dp->cmd.data |=
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((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
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(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
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MXS_DMA_DESC_HALT_ON_TERMINATE |
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MXS_DMA_DESC_TERMINATE_FLUSH;
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data += tl;
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length -= tl;
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if (!length) {
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dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
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if (flags & SPI_XFER_END) {
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ctrl0 &= ~SSP_CTRL0_LOCK_CS;
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ctrl0 |= SSP_CTRL0_IGNORE_CRC;
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}
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}
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/*
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* Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
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* case of MX28, write only CTRL0 in case of MX23 due
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* to the difference in register layout. It is utterly
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* essential that the XFER_SIZE register is written on
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* a per-descriptor basis with the same size as is the
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* descriptor!
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*/
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dp->cmd.pio_words[0] = ctrl0;
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#ifdef CONFIG_MX28
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dp->cmd.pio_words[1] = 0;
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dp->cmd.pio_words[2] = 0;
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dp->cmd.pio_words[3] = tl;
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#endif
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mxs_dma_desc_append(dmach, dp);
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dp++;
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}
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if (mxs_dma_go(dmach))
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ret = -EINVAL;
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/* The data arrived into DRAM, invalidate cache over them */
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if (!write)
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invalidate_dcache_range(dstart, dstart + cache_data_count);
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return ret;
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}
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int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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int len = bitlen / 8;
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char dummy;
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int write = 0;
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char *data = NULL;
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int dma = 1;
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if (bitlen == 0) {
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if (flags & SPI_XFER_END) {
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din = (void *)&dummy;
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len = 1;
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} else
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return 0;
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}
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/* Half-duplex only */
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if (din && dout)
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return -EINVAL;
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/* No data */
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if (!din && !dout)
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return 0;
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if (dout) {
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data = (char *)dout;
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write = 1;
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} else if (din) {
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data = (char *)din;
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write = 0;
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}
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/*
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* Check for alignment, if the buffer is aligned, do DMA transfer,
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* PIO otherwise. This is a temporary workaround until proper bounce
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* buffer is in place.
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*/
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if (dma) {
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if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
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dma = 0;
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if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
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dma = 0;
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}
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if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
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return mxs_spi_xfer_pio(priv, data, len, write, flags);
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} else {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
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return mxs_spi_xfer_dma(priv, data, len, write, flags);
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}
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}
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static int mxs_spi_probe(struct udevice *bus)
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{
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struct mxs_spi_plat *plat = dev_get_plat(bus);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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int ret;
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debug("%s: probe\n", __func__);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_fsl_imx23_spi *dtplat = &plat->dtplat;
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struct phandle_1_arg *p1a = &dtplat->clocks[0];
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priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
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priv->dma_channel = dtplat->dmas[1];
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priv->clk_id = p1a->arg[0];
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priv->max_freq = dtplat->spi_max_frequency;
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plat->num_cs = dtplat->num_cs;
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debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n",
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(unsigned int)priv->regs, priv->max_freq, priv->clk_id);
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#else
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priv->regs = (struct mxs_ssp_regs *)plat->base;
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priv->max_freq = plat->frequency;
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priv->dma_channel = plat->dma_id;
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priv->clk_id = plat->clk_id;
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#endif
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mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg);
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ret = mxs_dma_init_channel(priv->dma_channel);
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if (ret) {
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printf("%s: DMA init channel error %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int mxs_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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int cs = spi_chip_select(dev);
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/*
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* i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
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* To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
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* where:
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*
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* WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
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* WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
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* HW_SSP_CTRL0
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* SSn0 b00
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* SSn1 b01
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* SSn2 b10 (which require setting WAIT_FOR_IRQ)
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*
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* However, for now i.MX28 SPI driver will support up till 2 CSes
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* (SSn0, and SSn1).
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*/
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/* Ungate SSP clock and set active CS */
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clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
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BIT(MXS_SSP_CHIPSELECT_SHIFT) |
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SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
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return 0;
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}
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static int mxs_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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/* Gate SSP clock */
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setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
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return 0;
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}
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static int mxs_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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#ifdef CONFIG_MX28
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int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
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#else /* CONFIG_MX23 */
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int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
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#endif
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if (speed > priv->max_freq)
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speed = priv->max_freq;
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debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
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mxs_set_ssp_busclock(clkid, speed / 1000);
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return 0;
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}
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static int mxs_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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u32 reg;
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priv->mode = mode;
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debug("%s: mode 0x%x\n", __func__, mode);
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reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
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reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
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reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
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writel(reg, &ssp_regs->hw_ssp_ctrl1);
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/* Single bit SPI support */
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writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
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return 0;
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}
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static const struct dm_spi_ops mxs_spi_ops = {
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.claim_bus = mxs_spi_claim_bus,
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.release_bus = mxs_spi_release_bus,
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.xfer = mxs_spi_xfer,
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.set_speed = mxs_spi_set_speed,
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.set_mode = mxs_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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#if CONFIG_IS_ENABLED(OF_REAL)
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static int mxs_of_to_plat(struct udevice *bus)
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{
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struct mxs_spi_plat *plat = dev_get_plat(bus);
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u32 prop[2];
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int ret;
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plat->base = dev_read_addr(bus);
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plat->frequency =
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dev_read_u32_default(bus, "spi-max-frequency", 40000000);
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plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
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ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
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if (ret) {
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printf("%s: Reading 'dmas' property failed!\n", __func__);
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return ret;
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}
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plat->dma_id = prop[1];
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ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
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if (ret) {
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printf("%s: Reading 'clocks' property failed!\n", __func__);
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return ret;
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}
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plat->clk_id = prop[1];
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debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
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__func__, (uint)plat->base, plat->frequency, plat->num_cs,
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plat->dma_id, plat->clk_id);
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return 0;
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}
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static const struct udevice_id mxs_spi_ids[] = {
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{ .compatible = "fsl,imx23-spi" },
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{ .compatible = "fsl,imx28-spi" },
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{ }
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};
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#endif
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U_BOOT_DRIVER(fsl_imx23_spi) = {
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.name = "fsl_imx23_spi",
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.id = UCLASS_SPI,
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#if CONFIG_IS_ENABLED(OF_REAL)
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.of_match = mxs_spi_ids,
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.of_to_plat = mxs_of_to_plat,
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#endif
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.plat_auto = sizeof(struct mxs_spi_plat),
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.ops = &mxs_spi_ops,
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.priv_auto = sizeof(struct mxs_spi_priv),
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.probe = mxs_spi_probe,
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};
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DM_DRIVER_ALIAS(fsl_imx23_spi, fsl_imx28_spi)
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