mirror of
https://github.com/AsahiLinux/u-boot
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15713fc855
These files reference SZ_ macros without including <linux/sizes.h>, correct this. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
702 lines
18 KiB
C
702 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All Rights Reserved.
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*
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* Author: SkyLake.Huang <skylake.huang@mediatek.com>
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*/
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#include <clk.h>
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#include <cpu_func.h>
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#include <div64.h>
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#include <dm.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <stdbool.h>
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#include <watchdog.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#define SPI_CFG0_REG 0x0000
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#define SPI_CFG1_REG 0x0004
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#define SPI_TX_SRC_REG 0x0008
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#define SPI_RX_DST_REG 0x000c
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#define SPI_TX_DATA_REG 0x0010
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#define SPI_RX_DATA_REG 0x0014
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#define SPI_CMD_REG 0x0018
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#define SPI_IRQ_REG 0x001c
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#define SPI_STATUS_REG 0x0020
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#define SPI_PAD_SEL_REG 0x0024
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#define SPI_CFG2_REG 0x0028
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#define SPI_TX_SRC_REG_64 0x002c
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#define SPI_RX_DST_REG_64 0x0030
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#define SPI_CFG3_IPM_REG 0x0040
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
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#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
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#define SPI_CFG1_GET_TICKDLY_OFFSET 29
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#define SPI_CFG1_GET_TICKDLY_MASK GENMASK(31, 29)
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
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#define SPI_CFG2_SCK_HIGH_OFFSET 0
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#define SPI_CFG2_SCK_LOW_OFFSET 16
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#define SPI_CFG2_SCK_HIGH_MASK GENMASK(15, 0)
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#define SPI_CFG2_SCK_LOW_MASK GENMASK(31, 16)
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#define SPI_CMD_ACT BIT(0)
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#define SPI_CMD_RESUME BIT(1)
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#define SPI_CMD_RST BIT(2)
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#define SPI_CMD_PAUSE_EN BIT(4)
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#define SPI_CMD_DEASSERT BIT(5)
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#define SPI_CMD_SAMPLE_SEL BIT(6)
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#define SPI_CMD_CS_POL BIT(7)
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#define SPI_CMD_CPHA BIT(8)
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#define SPI_CMD_CPOL BIT(9)
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#define SPI_CMD_RX_DMA BIT(10)
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#define SPI_CMD_TX_DMA BIT(11)
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#define SPI_CMD_TXMSBF BIT(12)
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#define SPI_CMD_RXMSBF BIT(13)
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#define SPI_CMD_RX_ENDIAN BIT(14)
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#define SPI_CMD_TX_ENDIAN BIT(15)
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#define SPI_CMD_FINISH_IE BIT(16)
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#define SPI_CMD_PAUSE_IE BIT(17)
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#define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
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#define SPI_CMD_IPM_SPIM_LOOP BIT(21)
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#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
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#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
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#define PIN_MODE_CFG(x) ((x) / 2)
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#define SPI_CFG3_IPM_PIN_MODE_OFFSET 0
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#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
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#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
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#define SPI_CFG3_IPM_XMODE_EN BIT(4)
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#define SPI_CFG3_IPM_NODATA_FLAG BIT(5)
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#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8
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#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12
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#define SPI_CFG3_IPM_DUMMY_BYTELEN_OFFSET 16
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#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0)
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#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8)
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#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12)
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#define SPI_CFG3_IPM_DUMMY_BYTELEN_MASK GENMASK(19, 16)
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#define MT8173_SPI_MAX_PAD_SEL 3
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#define MTK_SPI_PAUSE_INT_STATUS 0x2
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#define MTK_SPI_IDLE 0
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#define MTK_SPI_PAUSED 1
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#define MTK_SPI_MAX_FIFO_SIZE 32U
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#define MTK_SPI_PACKET_SIZE 1024
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#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
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#define MTK_SPI_IPM_PACKET_LOOP SZ_256
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#define MTK_SPI_32BITS_MASK 0xffffffff
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#define DMA_ADDR_EXT_BITS 36
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#define DMA_ADDR_DEF_BITS 32
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#define CLK_TO_US(freq, clkcnt) DIV_ROUND_UP((clkcnt), (freq) / 1000000)
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/* struct mtk_spim_capability
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* @enhance_timing: Some IC design adjust cfg register to enhance time accuracy
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* @dma_ext: Some IC support DMA addr extension
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* @ipm_design: The IPM IP design improves some features, and supports dual/quad mode
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* @support_quad: Whether quad mode is supported
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*/
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struct mtk_spim_capability {
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bool enhance_timing;
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bool dma_ext;
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bool ipm_design;
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bool support_quad;
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};
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/* struct mtk_spim_priv
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* @base: Base address of the spi controller
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* @state: Controller state
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* @sel_clk: Pad clock
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* @spi_clk: Core clock
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* @xfer_len: Current length of data for transfer
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* @hw_cap: Controller capabilities
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* @tick_dly: Used to postpone SPI sampling time
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* @sample_sel: Sample edge of MISO
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* @dev: udevice of this spi controller
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* @tx_dma: Tx DMA address
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* @rx_dma: Rx DMA address
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*/
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struct mtk_spim_priv {
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void __iomem *base;
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u32 state;
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struct clk sel_clk, spi_clk;
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u32 xfer_len;
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struct mtk_spim_capability hw_cap;
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u32 tick_dly;
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u32 sample_sel;
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struct device *dev;
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dma_addr_t tx_dma;
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dma_addr_t rx_dma;
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};
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static void mtk_spim_reset(struct mtk_spim_priv *priv)
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{
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/* set the software reset bit in SPI_CMD_REG. */
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setbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST);
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clrbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST);
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}
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static int mtk_spim_hw_init(struct spi_slave *slave)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_spim_priv *priv = dev_get_priv(bus);
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u16 cpha, cpol;
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u32 reg_val;
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cpha = slave->mode & SPI_CPHA ? 1 : 0;
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cpol = slave->mode & SPI_CPOL ? 1 : 0;
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if (priv->hw_cap.enhance_timing) {
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if (priv->hw_cap.ipm_design) {
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/* CFG3 reg only used for spi-mem,
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* here write to default value
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*/
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writel(0x0, priv->base + SPI_CFG3_IPM_REG);
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clrsetbits_le32(priv->base + SPI_CMD_REG,
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SPI_CMD_IPM_GET_TICKDLY_MASK,
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priv->tick_dly <<
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SPI_CMD_IPM_GET_TICKDLY_OFFSET);
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} else {
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clrsetbits_le32(priv->base + SPI_CFG1_REG,
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SPI_CFG1_GET_TICKDLY_MASK,
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priv->tick_dly <<
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SPI_CFG1_GET_TICKDLY_OFFSET);
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}
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}
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reg_val = readl(priv->base + SPI_CMD_REG);
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if (priv->hw_cap.ipm_design) {
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/* SPI transfer without idle time until packet length done */
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reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
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if (slave->mode & SPI_LOOP)
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reg_val |= SPI_CMD_IPM_SPIM_LOOP;
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else
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reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
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}
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if (cpha)
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reg_val |= SPI_CMD_CPHA;
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else
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reg_val &= ~SPI_CMD_CPHA;
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if (cpol)
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reg_val |= SPI_CMD_CPOL;
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else
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reg_val &= ~SPI_CMD_CPOL;
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/* set the mlsbx and mlsbtx */
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if (slave->mode & SPI_LSB_FIRST) {
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reg_val &= ~SPI_CMD_TXMSBF;
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reg_val &= ~SPI_CMD_RXMSBF;
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} else {
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reg_val |= SPI_CMD_TXMSBF;
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reg_val |= SPI_CMD_RXMSBF;
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}
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/* do not reverse tx/rx endian */
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reg_val &= ~SPI_CMD_TX_ENDIAN;
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reg_val &= ~SPI_CMD_RX_ENDIAN;
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if (priv->hw_cap.enhance_timing) {
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/* set CS polarity */
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if (slave->mode & SPI_CS_HIGH)
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reg_val |= SPI_CMD_CS_POL;
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else
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reg_val &= ~SPI_CMD_CS_POL;
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if (priv->sample_sel)
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reg_val |= SPI_CMD_SAMPLE_SEL;
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else
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reg_val &= ~SPI_CMD_SAMPLE_SEL;
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}
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/* disable dma mode */
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reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
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/* disable deassert mode */
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reg_val &= ~SPI_CMD_DEASSERT;
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writel(reg_val, priv->base + SPI_CMD_REG);
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return 0;
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}
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static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
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u32 speed_hz)
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{
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u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
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spi_clk_hz = clk_get_rate(&priv->spi_clk);
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if (speed_hz <= spi_clk_hz / 4)
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div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
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else
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div = 4;
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sck_time = (div + 1) / 2;
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cs_time = sck_time * 2;
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if (priv->hw_cap.enhance_timing) {
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reg_val = ((sck_time - 1) & 0xffff)
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<< SPI_CFG2_SCK_HIGH_OFFSET;
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reg_val |= ((sck_time - 1) & 0xffff)
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<< SPI_CFG2_SCK_LOW_OFFSET;
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writel(reg_val, priv->base + SPI_CFG2_REG);
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reg_val = ((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET;
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reg_val |= ((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET;
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writel(reg_val, priv->base + SPI_CFG0_REG);
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} else {
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reg_val = ((sck_time - 1) & 0xff)
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<< SPI_CFG0_SCK_HIGH_OFFSET;
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reg_val |= ((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET;
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reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET;
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reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET;
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writel(reg_val, priv->base + SPI_CFG0_REG);
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}
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reg_val = readl(priv->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
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reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET;
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writel(reg_val, priv->base + SPI_CFG1_REG);
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}
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/**
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* mtk_spim_setup_packet() - setup packet format.
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* @priv: controller priv
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*
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* This controller sents/receives data in packets. The packet size is
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* configurable.
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*
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* This function calculates the maximum packet size available for current
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* data, and calculates the number of packets required to sent/receive data
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* as much as possible.
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*/
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static void mtk_spim_setup_packet(struct mtk_spim_priv *priv)
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{
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u32 packet_size, packet_loop, reg_val;
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/* Calculate maximum packet size */
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if (priv->hw_cap.ipm_design)
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packet_size = min_t(u32,
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priv->xfer_len,
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MTK_SPI_IPM_PACKET_SIZE);
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else
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packet_size = min_t(u32,
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priv->xfer_len,
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MTK_SPI_PACKET_SIZE);
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/* Calculates number of packets to sent/receive */
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packet_loop = priv->xfer_len / packet_size;
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reg_val = readl(priv->base + SPI_CFG1_REG);
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if (priv->hw_cap.ipm_design)
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reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
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else
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reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
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reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
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reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
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reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
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writel(reg_val, priv->base + SPI_CFG1_REG);
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}
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static void mtk_spim_enable_transfer(struct mtk_spim_priv *priv)
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{
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u32 cmd;
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cmd = readl(priv->base + SPI_CMD_REG);
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if (priv->state == MTK_SPI_IDLE)
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cmd |= SPI_CMD_ACT;
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else
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cmd |= SPI_CMD_RESUME;
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writel(cmd, priv->base + SPI_CMD_REG);
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}
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static bool mtk_spim_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_spim_priv *priv = dev_get_priv(bus);
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if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 ||
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op->addr.buswidth > 4 || op->dummy.buswidth > 4 ||
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op->data.buswidth > 4)
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return false;
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if (!priv->hw_cap.support_quad && (op->cmd.buswidth > 2 ||
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op->addr.buswidth > 2 || op->dummy.buswidth > 2 ||
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op->data.buswidth > 2))
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return false;
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if (op->addr.nbytes && op->dummy.nbytes &&
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op->addr.buswidth != op->dummy.buswidth)
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return false;
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if (op->addr.nbytes + op->dummy.nbytes > 16)
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return false;
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if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
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if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
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MTK_SPI_IPM_PACKET_LOOP ||
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op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
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return false;
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}
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return true;
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}
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static void mtk_spim_setup_dma_xfer(struct mtk_spim_priv *priv,
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const struct spi_mem_op *op)
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{
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writel((u32)(priv->tx_dma & MTK_SPI_32BITS_MASK),
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priv->base + SPI_TX_SRC_REG);
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if (priv->hw_cap.dma_ext)
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writel((u32)(priv->tx_dma >> 32),
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priv->base + SPI_TX_SRC_REG_64);
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if (op->data.dir == SPI_MEM_DATA_IN) {
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writel((u32)(priv->rx_dma & MTK_SPI_32BITS_MASK),
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priv->base + SPI_RX_DST_REG);
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if (priv->hw_cap.dma_ext)
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writel((u32)(priv->rx_dma >> 32),
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priv->base + SPI_RX_DST_REG_64);
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}
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}
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static int mtk_spim_transfer_wait(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_spim_priv *priv = dev_get_priv(bus);
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u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
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ulong us = 1;
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int ret = 0;
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if (op->data.dir == SPI_MEM_NO_DATA)
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clk_count = 32;
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else
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clk_count = op->data.nbytes;
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spi_bus_clk = clk_get_rate(&priv->spi_clk);
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sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
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sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
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do_div(spi_bus_clk, sck_l + sck_h + 2);
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us = CLK_TO_US(spi_bus_clk, clk_count * 8);
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us += 1000 * 1000; /* 1s tolerance */
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if (us > UINT_MAX)
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us = UINT_MAX;
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ret = readl_poll_timeout(priv->base + SPI_STATUS_REG, reg,
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reg & 0x1, us);
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if (ret < 0) {
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dev_err(priv->dev, "transfer timeout, val: 0x%lx\n", us);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int mtk_spim_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_spim_priv *priv = dev_get_priv(bus);
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u32 reg_val, nio = 1, tx_size;
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char *tx_tmp_buf;
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char *rx_tmp_buf;
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int i, ret = 0;
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mtk_spim_reset(priv);
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mtk_spim_hw_init(slave);
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mtk_spim_prepare_transfer(priv, slave->max_hz);
|
|
|
|
reg_val = readl(priv->base + SPI_CFG3_IPM_REG);
|
|
/* opcode byte len */
|
|
reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
|
|
reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
|
|
|
|
/* addr & dummy byte len */
|
|
if (op->addr.nbytes || op->dummy.nbytes)
|
|
reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
|
|
SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
|
|
|
|
/* data byte len */
|
|
if (!op->data.nbytes) {
|
|
reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
|
|
writel(0, priv->base + SPI_CFG1_REG);
|
|
} else {
|
|
reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
|
|
priv->xfer_len = op->data.nbytes;
|
|
mtk_spim_setup_packet(priv);
|
|
}
|
|
|
|
if (op->addr.nbytes || op->dummy.nbytes) {
|
|
if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
|
|
reg_val |= SPI_CFG3_IPM_XMODE_EN;
|
|
else
|
|
reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
|
|
}
|
|
|
|
if (op->addr.buswidth == 2 ||
|
|
op->dummy.buswidth == 2 ||
|
|
op->data.buswidth == 2)
|
|
nio = 2;
|
|
else if (op->addr.buswidth == 4 ||
|
|
op->dummy.buswidth == 4 ||
|
|
op->data.buswidth == 4)
|
|
nio = 4;
|
|
|
|
reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
|
|
reg_val |= PIN_MODE_CFG(nio) << SPI_CFG3_IPM_PIN_MODE_OFFSET;
|
|
|
|
reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
|
reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
|
|
else
|
|
reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
|
|
writel(reg_val, priv->base + SPI_CFG3_IPM_REG);
|
|
|
|
tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
|
|
if (op->data.dir == SPI_MEM_DATA_OUT)
|
|
tx_size += op->data.nbytes;
|
|
|
|
tx_size = max(tx_size, (u32)32);
|
|
|
|
/* Fill up tx data */
|
|
tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL);
|
|
if (!tx_tmp_buf) {
|
|
ret = -ENOMEM;
|
|
goto exit;
|
|
}
|
|
|
|
tx_tmp_buf[0] = op->cmd.opcode;
|
|
|
|
if (op->addr.nbytes) {
|
|
for (i = 0; i < op->addr.nbytes; i++)
|
|
tx_tmp_buf[i + 1] = op->addr.val >>
|
|
(8 * (op->addr.nbytes - i - 1));
|
|
}
|
|
|
|
if (op->dummy.nbytes)
|
|
memset(tx_tmp_buf + op->addr.nbytes + 1, 0xff,
|
|
op->dummy.nbytes);
|
|
|
|
if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
|
|
memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
|
|
op->data.buf.out, op->data.nbytes);
|
|
/* Finish filling up tx data */
|
|
|
|
priv->tx_dma = dma_map_single(tx_tmp_buf, tx_size, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(priv->dev, priv->tx_dma)) {
|
|
ret = -ENOMEM;
|
|
goto tx_free;
|
|
}
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN) {
|
|
if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
|
|
rx_tmp_buf = kzalloc(op->data.nbytes, GFP_KERNEL);
|
|
if (!rx_tmp_buf) {
|
|
ret = -ENOMEM;
|
|
goto tx_unmap;
|
|
}
|
|
} else {
|
|
rx_tmp_buf = op->data.buf.in;
|
|
}
|
|
|
|
priv->rx_dma = dma_map_single(rx_tmp_buf, op->data.nbytes,
|
|
DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(priv->dev, priv->rx_dma)) {
|
|
ret = -ENOMEM;
|
|
goto rx_free;
|
|
}
|
|
}
|
|
|
|
reg_val = readl(priv->base + SPI_CMD_REG);
|
|
reg_val |= SPI_CMD_TX_DMA;
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
|
reg_val |= SPI_CMD_RX_DMA;
|
|
|
|
writel(reg_val, priv->base + SPI_CMD_REG);
|
|
|
|
mtk_spim_setup_dma_xfer(priv, op);
|
|
|
|
mtk_spim_enable_transfer(priv);
|
|
|
|
/* Wait for the interrupt. */
|
|
ret = mtk_spim_transfer_wait(slave, op);
|
|
if (ret)
|
|
goto rx_unmap;
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN &&
|
|
!IS_ALIGNED((size_t)op->data.buf.in, 4))
|
|
memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
|
|
|
|
rx_unmap:
|
|
/* spi disable dma */
|
|
reg_val = readl(priv->base + SPI_CMD_REG);
|
|
reg_val &= ~SPI_CMD_TX_DMA;
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
|
reg_val &= ~SPI_CMD_RX_DMA;
|
|
writel(reg_val, priv->base + SPI_CMD_REG);
|
|
|
|
writel(0, priv->base + SPI_TX_SRC_REG);
|
|
writel(0, priv->base + SPI_RX_DST_REG);
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
|
dma_unmap_single(priv->rx_dma,
|
|
op->data.nbytes, DMA_FROM_DEVICE);
|
|
rx_free:
|
|
if (op->data.dir == SPI_MEM_DATA_IN &&
|
|
!IS_ALIGNED((size_t)op->data.buf.in, 4))
|
|
kfree(rx_tmp_buf);
|
|
tx_unmap:
|
|
dma_unmap_single(priv->tx_dma,
|
|
tx_size, DMA_TO_DEVICE);
|
|
tx_free:
|
|
kfree(tx_tmp_buf);
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_spim_adjust_op_size(struct spi_slave *slave,
|
|
struct spi_mem_op *op)
|
|
{
|
|
int opcode_len;
|
|
|
|
if (!op->data.nbytes)
|
|
return 0;
|
|
|
|
if (op->data.dir != SPI_MEM_NO_DATA) {
|
|
opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
|
|
if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
|
|
op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
|
|
/* force data buffer dma-aligned. */
|
|
op->data.nbytes -= op->data.nbytes % 4;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_spim_get_attr(struct mtk_spim_priv *priv, struct udevice *dev)
|
|
{
|
|
int ret;
|
|
|
|
priv->hw_cap.enhance_timing = dev_read_bool(dev, "enhance_timing");
|
|
priv->hw_cap.dma_ext = dev_read_bool(dev, "dma_ext");
|
|
priv->hw_cap.ipm_design = dev_read_bool(dev, "ipm_design");
|
|
priv->hw_cap.support_quad = dev_read_bool(dev, "support_quad");
|
|
|
|
ret = dev_read_u32(dev, "tick_dly", &priv->tick_dly);
|
|
if (ret < 0)
|
|
dev_err(priv->dev, "tick dly not set.\n");
|
|
|
|
ret = dev_read_u32(dev, "sample_sel", &priv->sample_sel);
|
|
if (ret < 0)
|
|
dev_err(priv->dev, "sample sel not set.\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_spim_probe(struct udevice *dev)
|
|
{
|
|
struct mtk_spim_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
priv->base = (void __iomem *)devfdt_get_addr(dev);
|
|
if (!priv->base)
|
|
return -EINVAL;
|
|
|
|
mtk_spim_get_attr(priv, dev);
|
|
|
|
ret = clk_get_by_name(dev, "sel-clk", &priv->sel_clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get sel-clk\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_get_by_name(dev, "spi-clk", &priv->spi_clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get spi-clk\n");
|
|
return ret;
|
|
}
|
|
|
|
clk_enable(&priv->sel_clk);
|
|
clk_enable(&priv->spi_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_spim_set_speed(struct udevice *dev, uint speed)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_spim_set_mode(struct udevice *dev, uint mode)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops mtk_spim_mem_ops = {
|
|
.adjust_op_size = mtk_spim_adjust_op_size,
|
|
.supports_op = mtk_spim_supports_op,
|
|
.exec_op = mtk_spim_exec_op
|
|
};
|
|
|
|
static const struct dm_spi_ops mtk_spim_ops = {
|
|
.mem_ops = &mtk_spim_mem_ops,
|
|
.set_speed = mtk_spim_set_speed,
|
|
.set_mode = mtk_spim_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id mtk_spim_ids[] = {
|
|
{ .compatible = "mediatek,ipm-spi" },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(mtk_spim) = {
|
|
.name = "mtk_spim",
|
|
.id = UCLASS_SPI,
|
|
.of_match = mtk_spim_ids,
|
|
.ops = &mtk_spim_ops,
|
|
.priv_auto = sizeof(struct mtk_spim_priv),
|
|
.probe = mtk_spim_probe,
|
|
};
|