mirror of
https://github.com/AsahiLinux/u-boot
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2ba1bd1e11
IPROC qspi driver supports both BSPI and MSPI modes. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Roman Bacik <roman.bacik@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
576 lines
15 KiB
C
576 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020-2021 Broadcom
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*/
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#include <common.h>
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#include <dm.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#include <linux/log2.h>
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/* Delay required to change the mode of operation */
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#define BUSY_DELAY_US 1
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#define BUSY_TIMEOUT_US 200000
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#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3))
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/* Chip attributes */
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#define QSPI_AXI_CLK 175000000
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#define SPBR_MIN 8U
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#define SPBR_MAX 255U
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#define NUM_CDRAM 16U
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#define CDRAM_PCS0 2
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#define CDRAM_CONT BIT(7)
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#define CDRAM_BITS_EN BIT(6)
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#define CDRAM_QUAD_MODE BIT(8)
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#define CDRAM_RBIT_INPUT BIT(10)
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#define MSPI_SPE BIT(6)
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#define MSPI_CONT_AFTER_CMD BIT(7)
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#define MSPI_MSTR BIT(7)
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/* Register fields */
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#define MSPI_SPCR0_MSB_BITS_8 0x00000020
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#define BSPI_RAF_CONTROL_START_MASK 0x00000001
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#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
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#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
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#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3
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#define BSPI_STRAP_OVERRIDE_4BYTE_SHIFT 2
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#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1
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#define BSPI_STRAP_OVERRIDE_SHIFT 0
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#define BSPI_BPC_DATA_SHIFT 0
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#define BSPI_BPC_MODE_SHIFT 8
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#define BSPI_BPC_ADDR_SHIFT 16
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#define BSPI_BPC_CMD_SHIFT 24
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#define BSPI_BPP_ADDR_SHIFT 16
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/* MSPI registers */
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#define MSPI_SPCR0_LSB_REG 0x000
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#define MSPI_SPCR0_MSB_REG 0x004
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#define MSPI_SPCR1_LSB_REG 0x008
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#define MSPI_SPCR1_MSB_REG 0x00c
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#define MSPI_NEWQP_REG 0x010
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#define MSPI_ENDQP_REG 0x014
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#define MSPI_SPCR2_REG 0x018
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#define MSPI_STATUS_REG 0x020
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#define MSPI_CPTQP_REG 0x024
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#define MSPI_TX_REG 0x040
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#define MSPI_RX_REG 0x0c0
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#define MSPI_CDRAM_REG 0x140
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#define MSPI_WRITE_LOCK_REG 0x180
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#define MSPI_DISABLE_FLUSH_GEN_REG 0x184
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/* BSPI registers */
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#define BSPI_REVISION_ID_REG 0x000
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#define BSPI_SCRATCH_REG 0x004
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#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
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#define BSPI_BUSY_STATUS_REG 0x00c
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#define BSPI_INTR_STATUS_REG 0x010
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#define BSPI_B0_STATUS_REG 0x014
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#define BSPI_B0_CTRL_REG 0x018
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#define BSPI_B1_STATUS_REG 0x01c
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#define BSPI_B1_CTRL_REG 0x020
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#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024
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#define BSPI_FLEX_MODE_ENABLE_REG 0x028
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#define BSPI_BITS_PER_CYCLE_REG 0x02C
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#define BSPI_BITS_PER_PHASE_REG 0x030
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#define BSPI_CMD_AND_MODE_BYTE_REG 0x034
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#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038
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#define BSPI_XOR_VALUE_REG 0x03C
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#define BSPI_XOR_ENABLE_REG 0x040
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#define BSPI_PIO_MODE_ENABLE_REG 0x044
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#define BSPI_PIO_IODIR_REG 0x048
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#define BSPI_PIO_DATA_REG 0x04C
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/* RAF registers */
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#define BSPI_RAF_START_ADDRESS_REG 0x00
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#define BSPI_RAF_NUM_WORDS_REG 0x04
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#define BSPI_RAF_CTRL_REG 0x08
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#define BSPI_RAF_FULLNESS_REG 0x0C
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#define BSPI_RAF_WATERMARK_REG 0x10
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#define BSPI_RAF_STATUS_REG 0x14
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#define BSPI_RAF_READ_DATA_REG 0x18
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#define BSPI_RAF_WORD_CNT_REG 0x1C
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#define BSPI_RAF_CURR_ADDR_REG 0x20
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#define XFER_DUAL BIT(30)
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#define XFER_QUAD BIT(31)
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#define FLUSH_BIT BIT(0)
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#define MAST_N_BOOT_BIT BIT(0)
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#define WRITE_LOCK_BIT BIT(0)
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#define CEIL(m, n) (((m) + (n) - 1) / (n))
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#define UPPER_BYTE_MASK 0xFF000000
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#define SIZE_16MB 0x001000000
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/*
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* struct bcmspi_priv - qspi private structure
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*
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* @bspi_addr: bspi read address
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* @bspi_4byte_addr: bspi 4 byte address mode
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* @mspi: mspi registers block address
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* @bspi: bspi registers block address
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* @bspi_raf: bspi raf registers block address
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*/
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struct bcmspi_priv {
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u32 bspi_addr;
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bool bspi_4byte_addr;
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fdt_addr_t mspi;
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fdt_addr_t bspi;
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fdt_addr_t bspi_raf;
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};
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/* BSPI mode */
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static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
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{
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writel(0, priv->bspi + BSPI_B0_CTRL_REG);
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writel(0, priv->bspi + BSPI_B1_CTRL_REG);
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writel(FLUSH_BIT, priv->bspi + BSPI_B0_CTRL_REG);
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writel(FLUSH_BIT, priv->bspi + BSPI_B1_CTRL_REG);
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}
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static int bspi_enable(struct bcmspi_priv *priv)
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{
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/* Disable write lock */
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writel(0, priv->mspi + MSPI_WRITE_LOCK_REG);
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/* Flush prefetch buffers */
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bspi_flush_prefetch_buffers(priv);
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/* Switch to BSPI */
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writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
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return 0;
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}
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static int bspi_disable(struct bcmspi_priv *priv)
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{
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int ret;
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uint val;
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if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
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ret = readl_poll_timeout(priv->bspi + BSPI_BUSY_STATUS_REG, val, !(val & 1),
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BUSY_TIMEOUT_US);
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if (ret) {
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printf("%s: Failed to disable bspi, device busy\n", __func__);
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return ret;
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}
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/* Switch to MSPI */
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writel(MAST_N_BOOT_BIT, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
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udelay(BUSY_DELAY_US);
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val = readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
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if (!(val & 1)) {
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printf("%s: Failed to enable mspi\n", __func__);
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return -EBUSY;
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}
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}
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/* Enable write lock */
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writel(WRITE_LOCK_BIT, priv->mspi + MSPI_WRITE_LOCK_REG);
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return 0;
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}
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static int bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes)
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{
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u32 status;
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uint words;
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int aligned;
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int ret;
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/*
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* Flush data from the previous session (unlikely)
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* Read outstanding bits in the poll condition to empty FIFO
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*/
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ret = readl_poll_timeout(priv->bspi_raf + BSPI_RAF_STATUS_REG,
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status,
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(!readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG) &&
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status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK) &&
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!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK),
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BUSY_TIMEOUT_US);
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if (ret) {
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printf("%s: Failed to flush fifo\n", __func__);
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return ret;
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}
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/* Transfer is in words */
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words = CEIL(bytes, 4);
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/* Setup hardware */
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if (priv->bspi_4byte_addr) {
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u32 val = priv->bspi_addr & UPPER_BYTE_MASK;
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if (val != readl(priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG)) {
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writel(val, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
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bspi_flush_prefetch_buffers(priv);
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}
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}
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writel(priv->bspi_addr & ~UPPER_BYTE_MASK, priv->bspi_raf + BSPI_RAF_START_ADDRESS_REG);
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writel(words, priv->bspi_raf + BSPI_RAF_NUM_WORDS_REG);
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writel(0, priv->bspi_raf + BSPI_RAF_WATERMARK_REG);
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/* Start reading */
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writel(BSPI_RAF_CONTROL_START_MASK, priv->bspi_raf + BSPI_RAF_CTRL_REG);
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aligned = DWORD_ALIGNED(rx);
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while (bytes) {
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status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
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if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
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/* RAF is LE only, convert data to host endianness */
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u32 data = le32_to_cpu(readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG));
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/* Check if we can use the whole word */
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if (aligned && bytes >= 4) {
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*(u32 *)rx = data;
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rx += 4;
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bytes -= 4;
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} else {
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uint chunk = min(bytes, 4U);
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/* Read out bytes one by one */
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while (chunk) {
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*rx++ = (u8)data;
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data >>= 8;
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chunk--;
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bytes--;
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}
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}
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continue;
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}
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if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) {
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/* FIFO is empty and the session is done */
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break;
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}
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}
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return 0;
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}
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static int bspi_read(struct bcmspi_priv *priv, u8 *rx, uint bytes)
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{
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int ret;
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/* Transfer data */
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while (bytes > 0) {
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/* Special handing since RAF cannot go across 16MB boundary */
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uint trans = bytes;
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/* Divide into multiple transfers if it goes across the 16MB boundary */
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if (priv->bspi_4byte_addr && (priv->bspi_addr >> 24) !=
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((priv->bspi_addr + bytes) >> 24))
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trans = SIZE_16MB - (priv->bspi_addr & ~UPPER_BYTE_MASK);
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ret = bspi_read_via_raf(priv, rx, trans);
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if (ret)
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return ret;
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priv->bspi_addr += trans;
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rx += trans;
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bytes -= trans;
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}
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bspi_flush_prefetch_buffers(priv);
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return 0;
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}
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static void bspi_set_flex_mode(struct bcmspi_priv *priv, const struct spi_mem_op *op)
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{
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int bpp = (op->dummy.nbytes * 8) / op->dummy.buswidth;
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int cmd = op->cmd.opcode;
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int bpc = ilog2(op->data.buswidth) << BSPI_BPC_DATA_SHIFT |
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ilog2(op->addr.buswidth) << BSPI_BPC_ADDR_SHIFT |
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ilog2(op->cmd.buswidth) << BSPI_BPC_CMD_SHIFT;
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int so = BIT(BSPI_STRAP_OVERRIDE_SHIFT) |
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(op->data.buswidth > 1) << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT |
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(op->addr.nbytes > 3) << BSPI_STRAP_OVERRIDE_4BYTE_SHIFT |
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(op->data.buswidth > 3) << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT;
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/* Disable flex mode first */
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writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
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/* Configure single, dual or quad mode */
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writel(bpc, priv->bspi + BSPI_BITS_PER_CYCLE_REG);
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/* Opcode */
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writel(cmd, priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
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/* Count of dummy cycles */
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writel(bpp, priv->bspi + BSPI_BITS_PER_PHASE_REG);
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/* Enable 4-byte address */
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if (priv->bspi_4byte_addr) {
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setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
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} else {
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clrbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
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writel(0, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
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}
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/* Enable flex mode to take effect */
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writel(1, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
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/* Flush prefetch buffers since 32MB window BSPI could be used */
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bspi_flush_prefetch_buffers(priv);
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/* Override the strap settings */
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writel(so, priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG);
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}
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static int bspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct bcmspi_priv *priv = dev_get_priv(bus);
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int ret = -ENOTSUPP;
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/* BSPI read */
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if (op->data.dir == SPI_MEM_DATA_IN &&
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op->data.nbytes && op->addr.nbytes) {
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priv->bspi_4byte_addr = (op->addr.nbytes > 3);
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priv->bspi_addr = op->addr.val;
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bspi_set_flex_mode(priv, op);
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ret = bspi_read(priv, op->data.buf.in, op->data.nbytes);
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}
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return ret;
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}
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static const struct spi_controller_mem_ops bspi_mem_ops = {
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.exec_op = bspi_exec_op,
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};
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/* MSPI mode */
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static int mspi_exec(struct bcmspi_priv *priv, uint bytes, const u8 *tx, u8 *rx, ulong flags)
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{
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u32 cdr = CDRAM_PCS0 | CDRAM_CONT;
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bool use_16bits = !(bytes & 1);
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if (flags & XFER_QUAD) {
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cdr |= CDRAM_QUAD_MODE;
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if (!tx)
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cdr |= CDRAM_RBIT_INPUT;
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}
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while (bytes) {
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uint chunk;
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uint queues;
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uint i;
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uint val;
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int ret;
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if (use_16bits) {
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chunk = min(bytes, NUM_CDRAM * 2);
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queues = (chunk + 1) / 2;
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bytes -= chunk;
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/* Fill CDRAMs */
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for (i = 0; i < queues; i++)
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writel(cdr | CDRAM_BITS_EN, priv->mspi + MSPI_CDRAM_REG + 4 * i);
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/* Fill TXRAMs */
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for (i = 0; i < chunk; i++)
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writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 4 * i);
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} else {
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/* Determine how many bytes to process this time */
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chunk = min(bytes, NUM_CDRAM);
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queues = chunk;
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bytes -= chunk;
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/* Fill CDRAMs and TXRAMS */
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for (i = 0; i < chunk; i++) {
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writel(cdr, priv->mspi + MSPI_CDRAM_REG + 4 * i);
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writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 8 * i);
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}
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}
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/* Setup queue pointers */
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writel(0, priv->mspi + MSPI_NEWQP_REG);
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writel(queues - 1, priv->mspi + MSPI_ENDQP_REG);
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/* Deassert CS if requested and it's the last transfer */
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if (bytes == 0 && (flags & SPI_XFER_END))
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clrbits_le32(priv->mspi + MSPI_CDRAM_REG + ((queues - 1) << 2), CDRAM_CONT);
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/* Kick off */
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writel(0, priv->mspi + MSPI_STATUS_REG);
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if (bytes == 0 && (flags & SPI_XFER_END))
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writel(MSPI_SPE, priv->mspi + MSPI_SPCR2_REG);
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else
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writel(MSPI_SPE | MSPI_CONT_AFTER_CMD,
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priv->mspi + MSPI_SPCR2_REG);
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ret = readl_poll_timeout(priv->mspi + MSPI_STATUS_REG, val, (val & 1),
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BUSY_TIMEOUT_US);
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if (ret) {
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printf("%s: Failed to disable bspi, device busy\n", __func__);
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return ret;
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}
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/* Read data out */
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if (rx) {
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if (use_16bits) {
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for (i = 0; i < chunk; i++)
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rx[i] = readl(priv->mspi + MSPI_RX_REG + 4 * i) & 0xff;
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} else {
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for (i = 0; i < chunk; i++)
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rx[i] = readl(priv->mspi + MSPI_RX_REG + 8 * i + 4) & 0xff;
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}
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}
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/* Advance pointers */
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if (tx)
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tx += chunk;
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if (rx)
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rx += chunk;
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}
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return 0;
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}
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static int mspi_xfer(struct udevice *dev, uint bitlen, const void *dout, void *din, ulong flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct bcmspi_priv *priv = dev_get_priv(bus);
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uint bytes;
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int ret = 0;
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/* we can only transfer multiples of 8 bits */
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if (bitlen % 8)
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return -EPROTONOSUPPORT;
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bytes = bitlen / 8;
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if (flags & SPI_XFER_BEGIN) {
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/* Switch to MSPI */
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ret = bspi_disable(priv);
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if (ret)
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return ret;
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}
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/* MSPI: Transfer */
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if (bytes)
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ret = mspi_exec(priv, bytes, dout, din, flags);
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if (flags & SPI_XFER_END) {
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/* Switch back to BSPI */
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ret = bspi_enable(priv);
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if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* iProc interface */
|
|
|
|
static int iproc_qspi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct bcmspi_priv *priv = dev_get_priv(bus);
|
|
uint spbr;
|
|
|
|
/* MSPI: SCK configuration */
|
|
spbr = (QSPI_AXI_CLK - 1) / (2 * speed) + 1;
|
|
writel(max(min(spbr, SPBR_MAX), SPBR_MIN), priv->mspi + MSPI_SPCR0_LSB_REG);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_qspi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct bcmspi_priv *priv = dev_get_priv(bus);
|
|
|
|
/* MSPI: set master bit and mode */
|
|
writel(MSPI_MSTR /* Master */ | (mode & 3), priv->mspi + MSPI_SPCR0_MSB_REG);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_qspi_claim_bus(struct udevice *dev)
|
|
{
|
|
/* Nothing to do */
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_qspi_release_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
struct bcmspi_priv *priv = dev_get_priv(bus);
|
|
|
|
/* Make sure no operation is in progress */
|
|
writel(0, priv->mspi + MSPI_SPCR2_REG);
|
|
udelay(BUSY_DELAY_US);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_qspi_of_to_plat(struct udevice *bus)
|
|
{
|
|
struct bcmspi_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->bspi = dev_read_addr_name(bus, "bspi");
|
|
if (IS_ERR((void *)priv->bspi)) {
|
|
printf("%s: Failed to get bspi base address\n", __func__);
|
|
return PTR_ERR((void *)priv->bspi);
|
|
}
|
|
|
|
priv->bspi_raf = dev_read_addr_name(bus, "bspi_raf");
|
|
if (IS_ERR((void *)priv->bspi_raf)) {
|
|
printf("%s: Failed to get bspi_raf base address\n", __func__);
|
|
return PTR_ERR((void *)priv->bspi_raf);
|
|
}
|
|
|
|
priv->mspi = dev_read_addr_name(bus, "mspi");
|
|
if (IS_ERR((void *)priv->mspi)) {
|
|
printf("%s: Failed to get mspi base address\n", __func__);
|
|
return PTR_ERR((void *)priv->mspi);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_qspi_probe(struct udevice *bus)
|
|
{
|
|
struct bcmspi_priv *priv = dev_get_priv(bus);
|
|
|
|
/* configure mspi */
|
|
writel(0, priv->mspi + MSPI_SPCR1_LSB_REG);
|
|
writel(0, priv->mspi + MSPI_SPCR1_MSB_REG);
|
|
writel(0, priv->mspi + MSPI_NEWQP_REG);
|
|
writel(0, priv->mspi + MSPI_ENDQP_REG);
|
|
writel(0, priv->mspi + MSPI_SPCR2_REG);
|
|
|
|
/* configure bspi */
|
|
bspi_enable(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops iproc_qspi_ops = {
|
|
.claim_bus = iproc_qspi_claim_bus,
|
|
.release_bus = iproc_qspi_release_bus,
|
|
.xfer = mspi_xfer,
|
|
.set_speed = iproc_qspi_set_speed,
|
|
.set_mode = iproc_qspi_set_mode,
|
|
.mem_ops = &bspi_mem_ops,
|
|
};
|
|
|
|
static const struct udevice_id iproc_qspi_ids[] = {
|
|
{ .compatible = "brcm,iproc-qspi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(iproc_qspi) = {
|
|
.name = "iproc_qspi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = iproc_qspi_ids,
|
|
.ops = &iproc_qspi_ops,
|
|
.of_to_plat = iproc_qspi_of_to_plat,
|
|
.priv_auto = sizeof(struct bcmspi_priv),
|
|
.probe = iproc_qspi_probe,
|
|
};
|