mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
577 lines
15 KiB
C
577 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Cortina SPI-FLASH Controller
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*
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* Copyright (C) 2020 Cortina Access Inc. All Rights Reserved.
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*
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* Author: PengPeng Chen <pengpeng.chen@cortina-access.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/compat.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/sizes.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <reset.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct ca_sflash_regs {
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u32 idr; /* 0x00:Flash word ID Register */
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u32 tc; /* 0x04:Flash Timeout Counter Register */
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u32 sr; /* 0x08:Flash Status Register */
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u32 tr; /* 0x0C:Flash Type Register */
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u32 asr; /* 0x10:Flash ACCESS START/BUSY Register */
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u32 isr; /* 0x14:Flash Interrupt Status Register */
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u32 imr; /* 0x18:Flash Interrupt Mask Register */
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u32 fcr; /* 0x1C:NAND Flash FIFO Control Register */
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u32 ffsr; /* 0x20:Flash FIFO Status Register */
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u32 ffar; /* 0x24:Flash FIFO ADDRESS Register */
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u32 ffmar; /* 0x28:Flash FIFO MATCHING ADDRESS Register */
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u32 ffdr; /* 0x2C:Flash FIFO Data Register */
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u32 ar; /* 0x30:Serial Flash Access Register */
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u32 ear; /* 0x34:Serial Flash Extend Access Register */
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u32 adr; /* 0x38:Serial Flash ADdress Register */
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u32 dr; /* 0x3C:Serial Flash Data Register */
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u32 tmr; /* 0x40:Serial Flash Timing Register */
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};
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/*
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* FLASH_TYPE
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*/
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#define CA_FLASH_TR_PIN BIT(15)
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#define CA_FLASH_TR_TYPE_MSK GENMASK(14, 12)
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#define CA_FLASH_TR_TYPE(tp) (((tp) << 12) & CA_FLASH_TR_TYPE_MSK)
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#define CA_FLASH_TR_WIDTH BIT(11)
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#define CA_FLASH_TR_SIZE_MSK GENMASK(10, 9)
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#define CA_FLASH_TR_SIZE(sz) (((sz) << 9) & CA_FLASH_TR_SIZE_MSK)
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/*
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* FLASH_FLASH_ACCESS_START
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*/
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#define CA_FLASH_ASR_IND_START_EN BIT(1)
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#define CA_FLASH_ASR_DMA_START_EN BIT(3)
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#define CA_FLASH_ASR_WR_ACCESS_EN BIT(9)
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/*
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* FLASH_FLASH_INTERRUPT
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*/
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#define CA_FLASH_ISR_REG_IRQ BIT(1)
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#define CA_FLASH_ISR_FIFO_IRQ BIT(2)
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/*
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* FLASH_SF_ACCESS
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*/
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#define CA_SF_AR_OP_MSK GENMASK(7, 0)
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#define CA_SF_AR_OP(op) ((op) << 0 & CA_SF_AR_OP_MSK)
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#define CA_SF_AR_ACCODE_MSK GENMASK(11, 8)
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#define CA_SF_AR_ACCODE(ac) (((ac) << 8) & CA_SF_AR_ACCODE_MSK)
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#define CA_SF_AR_FORCE_TERM BIT(12)
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#define CA_SF_AR_FORCE_BURST BIT(13)
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#define CA_SF_AR_AUTO_MODE_EN BIT(15)
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#define CA_SF_AR_CHIP_EN_ALT BIT(16)
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#define CA_SF_AR_HI_SPEED_RD BIT(17)
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#define CA_SF_AR_MIO_INF_DC BIT(24)
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#define CA_SF_AR_MIO_INF_AC BIT(25)
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#define CA_SF_AR_MIO_INF_CC BIT(26)
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#define CA_SF_AR_DDR_MSK GENMASK(29, 28)
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#define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK)
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#define CA_SF_AR_MIO_INF_MSK GENMASK(31, 30)
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#define CA_SF_AR_MIO_INF(io) (((io) << 30) & CA_SF_AR_MIO_INF_MSK)
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/*
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* FLASH_SF_EXT_ACCESS
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*/
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#define CA_SF_EAR_OP_MSK GENMASK(7, 0)
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#define CA_SF_EAR_OP(op) (((op) << 0) & CA_SF_EAR_OP_MSK)
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#define CA_SF_EAR_DATA_CNT_MSK GENMASK(20, 8)
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#define CA_SF_EAR_DATA_CNT(cnt) (((cnt) << 8) & CA_SF_EAR_DATA_CNT_MSK)
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#define CA_SF_EAR_DATA_CNT_MAX (4096)
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#define CA_SF_EAR_ADDR_CNT_MSK GENMASK(23, 21)
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#define CA_SF_EAR_ADDR_CNT(cnt) (((cnt) << 21) & CA_SF_EAR_ADDR_CNT_MSK)
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#define CA_SF_EAR_ADDR_CNT_MAX (5)
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#define CA_SF_EAR_DUMY_CNT_MSK GENMASK(29, 24)
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#define CA_SF_EAR_DUMY_CNT(cnt) (((cnt) << 24) & CA_SF_EAR_DUMY_CNT_MSK)
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#define CA_SF_EAR_DUMY_CNT_MAX (32)
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#define CA_SF_EAR_DRD_CMD_EN BIT(31)
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/*
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* FLASH_SF_ADDRESS
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*/
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#define CA_SF_ADR_REG_MSK GENMASK(31, 0)
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#define CA_SF_ADR_REG(addr) (((addr) << 0) & CA_SF_ADR_REG_MSK)
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/*
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* FLASH_SF_DATA
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*/
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#define CA_SF_DR_REG_MSK GENMASK(31, 0)
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#define CA_SF_DR_REG(addr) (((addr) << 0) & CA_SF_DR_REG_MSK)
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/*
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* FLASH_SF_TIMING
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*/
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#define CA_SF_TMR_IDLE_MSK GENMASK(7, 0)
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#define CA_SF_TMR_IDLE(idle) (((idle) << 0) & CA_SF_TMR_IDLE_MSK)
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#define CA_SF_TMR_HOLD_MSK GENMASK(15, 8)
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#define CA_SF_TMR_HOLD(hold) (((hold) << 8) & CA_SF_TMR_HOLD_MSK)
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#define CA_SF_TMR_SETUP_MSK GENMASK(23, 16)
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#define CA_SF_TMR_SETUP(setup) (((setup) << 16) & CA_SF_TMR_SETUP_MSK)
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#define CA_SF_TMR_CLK_MSK GENMASK(26, 24)
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#define CA_SF_TMR_CLK(clk) (((clk) << 24) & CA_SF_TMR_CLK_MSK)
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#define CA_SFLASH_IND_WRITE 0
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#define CA_SFLASH_IND_READ 1
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#define CA_SFLASH_MEM_MAP 3
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#define CA_SFLASH_FIFO_TIMEOUT_US 30000
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#define CA_SFLASH_BUSY_TIMEOUT_US 40000
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#define CA_SF_AC_OP 0x00
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#define CA_SF_AC_OP_1_DATA 0x01
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#define CA_SF_AC_OP_2_DATA 0x02
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#define CA_SF_AC_OP_3_DATA 0x03
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#define CA_SF_AC_OP_4_DATA 0x04
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#define CA_SF_AC_OP_3_ADDR 0x05
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#define CA_SF_AC_OP_4_ADDR (CA_SF_AC_OP_3_ADDR)
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#define CA_SF_AC_OP_3_ADDR_1_DATA 0x06
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#define CA_SF_AC_OP_4_ADDR_1_DATA (CA_SF_AC_OP_3_ADDR_1_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_2_DATA 0x07
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#define CA_SF_AC_OP_4_ADDR_2_DATA (CA_SF_AC_OP_3_ADDR_2_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_3_DATA 0x08
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#define CA_SF_AC_OP_4_ADDR_3_DATA (CA_SF_AC_OP_3_ADDR_3_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_4_DATA 0x09
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#define CA_SF_AC_OP_4_ADDR_4_DATA (CA_SF_AC_OP_3_ADDR_4_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_X_1_DATA 0x0A
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#define CA_SF_AC_OP_4_ADDR_X_1_DATA (CA_SF_AC_OP_3_ADDR_X_1_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_X_2_DATA 0x0B
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#define CA_SF_AC_OP_4_ADDR_X_2_DATA (CA_SF_AC_OP_3_ADDR_X_2_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_X_3_DATA 0x0C
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#define CA_SF_AC_OP_4_ADDR_X_3_DATA (CA_SF_AC_OP_3_ADDR_X_3_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_X_4_DATA 0x0D
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#define CA_SF_AC_OP_4_ADDR_X_4_DATA (CA_SF_AC_OP_3_ADDR_X_4_DATA << 2)
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#define CA_SF_AC_OP_3_ADDR_4X_1_DATA 0x0E
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#define CA_SF_AC_OP_4_ADDR_4X_1_DATA (CA_SF_AC_OP_3_ADDR_4X_1_DATA << 2)
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#define CA_SF_AC_OP_EXTEND 0x0F
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#define CA_SF_ACCESS_MIO_SINGLE 0
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#define CA_SF_ACCESS_MIO_DUAL 1
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#define CA_SF_ACCESS_MIO_QUARD 2
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enum access_type {
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RD_ACCESS,
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WR_ACCESS,
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};
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struct ca_sflash_priv {
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struct ca_sflash_regs *regs;
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u8 rx_width;
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u8 tx_width;
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};
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/*
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* This function doesn't do anything except help with debugging
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*/
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static int ca_sflash_claim_bus(struct udevice *dev)
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{
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debug("%s:\n", __func__);
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return 0;
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}
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static int ca_sflash_release_bus(struct udevice *dev)
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{
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debug("%s:\n", __func__);
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return 0;
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}
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static int ca_sflash_set_speed(struct udevice *dev, uint speed)
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{
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debug("%s:\n", __func__);
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return 0;
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}
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static int ca_sflash_set_mode(struct udevice *dev, uint mode)
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{
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struct ca_sflash_priv *priv = dev_get_priv(dev);
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if (mode & SPI_RX_QUAD)
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priv->rx_width = 4;
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else if (mode & SPI_RX_DUAL)
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priv->rx_width = 2;
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else
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priv->rx_width = 1;
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if (mode & SPI_TX_QUAD)
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priv->tx_width = 4;
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else if (mode & SPI_TX_DUAL)
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priv->tx_width = 2;
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else
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priv->tx_width = 1;
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debug("%s: mode=%d, rx_width=%d, tx_width=%d\n",
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__func__, mode, priv->rx_width, priv->tx_width);
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return 0;
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}
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static int _ca_sflash_wait_for_not_busy(struct ca_sflash_priv *priv)
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{
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u32 asr;
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if (readl_poll_timeout(&priv->regs->asr, asr,
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!(asr & CA_FLASH_ASR_IND_START_EN),
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CA_SFLASH_BUSY_TIMEOUT_US)) {
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pr_err("busy timeout (stat:%#x)\n", asr);
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return -1;
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}
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return 0;
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}
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static int _ca_sflash_wait_cmd(struct ca_sflash_priv *priv,
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enum access_type type)
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{
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if (type == WR_ACCESS) {
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/* Enable write access and start the sflash indirect access */
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clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
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CA_FLASH_ASR_WR_ACCESS_EN
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| CA_FLASH_ASR_IND_START_EN);
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} else if (type == RD_ACCESS) {
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/* Start the sflash indirect access */
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clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
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CA_FLASH_ASR_IND_START_EN);
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} else {
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printf("%s: !error access type.\n", __func__);
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return -1;
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}
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/* Wait til the action(rd/wr) completed */
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return _ca_sflash_wait_for_not_busy(priv);
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}
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static int _ca_sflash_read(struct ca_sflash_priv *priv,
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u8 *buf, unsigned int data_len)
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{
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u32 reg_data;
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int len;
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len = data_len;
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while (len >= 4) {
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if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
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return -1;
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reg_data = readl(&priv->regs->dr);
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*buf++ = reg_data & 0xFF;
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*buf++ = (reg_data >> 8) & 0xFF;
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*buf++ = (reg_data >> 16) & 0xFF;
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*buf++ = (reg_data >> 24) & 0xFF;
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len -= 4;
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debug("%s: reg_data=%#08x\n",
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__func__, reg_data);
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}
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if (len > 0) {
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if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
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return -1;
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reg_data = readl(&priv->regs->dr);
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debug("%s: reg_data=%#08x\n",
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__func__, reg_data);
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}
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switch (len) {
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case 3:
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*buf++ = reg_data & 0xFF;
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*buf++ = (reg_data >> 8) & 0xFF;
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*buf++ = (reg_data >> 16) & 0xFF;
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break;
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case 2:
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*buf++ = reg_data & 0xFF;
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*buf++ = (reg_data >> 8) & 0xFF;
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break;
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case 1:
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*buf++ = reg_data & 0xFF;
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break;
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case 0:
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break;
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default:
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printf("%s: error data_length %d!\n", __func__, len);
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}
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return 0;
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}
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static int _ca_sflash_mio_set(struct ca_sflash_priv *priv,
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u8 width)
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{
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if (width == 4) {
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setbits_le32(&priv->regs->ar,
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CA_SF_AR_MIO_INF_DC
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| CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_QUARD)
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| CA_SF_AR_FORCE_BURST);
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} else if (width == 2) {
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setbits_le32(&priv->regs->ar,
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CA_SF_AR_MIO_INF_DC
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| CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_DUAL)
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| CA_SF_AR_FORCE_BURST);
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} else if (width == 1) {
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setbits_le32(&priv->regs->ar,
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CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_SINGLE)
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| CA_SF_AR_FORCE_BURST);
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} else {
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printf("%s: error rx/tx width %d!\n", __func__, width);
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return -1;
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}
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return 0;
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}
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static int _ca_sflash_write(struct ca_sflash_priv *priv,
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u8 *buf, unsigned int data_len)
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{
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u32 reg_data;
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int len;
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len = data_len;
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while (len > 0) {
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reg_data = buf[0]
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| (buf[1] << 8)
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| (buf[2] << 16)
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| (buf[3] << 24);
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debug("%s: reg_data=%#08x\n",
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__func__, reg_data);
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/* Fill data */
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clrsetbits_le32(&priv->regs->dr, GENMASK(31, 0), reg_data);
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if (_ca_sflash_wait_cmd(priv, WR_ACCESS))
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return -1;
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len -= 4;
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buf += 4;
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}
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return 0;
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}
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static int _ca_sflash_access_data(struct ca_sflash_priv *priv,
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struct spi_mem_op *op)
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{
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int total_cnt;
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unsigned int len;
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unsigned int data_cnt = op->data.nbytes;
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u64 addr_offset = op->addr.val;
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u8 addr_cnt = op->addr.nbytes;
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u8 *data_buf = NULL;
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u8 *buf = NULL;
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if (op->data.dir == SPI_MEM_DATA_IN)
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data_buf = (u8 *)op->data.buf.in;
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else
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data_buf = (u8 *)op->data.buf.out;
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if (data_cnt > CA_SF_EAR_DATA_CNT_MAX)
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buf = malloc(CA_SF_EAR_DATA_CNT_MAX);
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else
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buf = malloc(data_cnt);
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total_cnt = data_cnt;
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while (total_cnt > 0) {
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/* Fill address */
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if (addr_cnt > 0)
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clrsetbits_le32(&priv->regs->adr,
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GENMASK(31, 0), (u32)addr_offset);
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if (total_cnt > CA_SF_EAR_DATA_CNT_MAX) {
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len = CA_SF_EAR_DATA_CNT_MAX;
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addr_offset += CA_SF_EAR_DATA_CNT_MAX;
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/* Clear start bit before next bulk read */
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clrbits_le32(&priv->regs->asr, GENMASK(31, 0));
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} else {
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len = total_cnt;
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}
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memset(buf, 0, len);
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if (op->data.dir == SPI_MEM_DATA_IN) {
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if (_ca_sflash_read(priv, buf, len))
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break;
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memcpy(data_buf, buf, len);
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} else {
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memcpy(buf, data_buf, len);
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if (_ca_sflash_write(priv, buf, len))
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break;
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}
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total_cnt -= len;
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data_buf += len;
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}
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if (buf)
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free(buf);
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return total_cnt > 0 ? -1 : 0;
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}
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static int _ca_sflash_issue_cmd(struct ca_sflash_priv *priv,
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struct spi_mem_op *op, u8 opcode)
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{
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u8 dummy_cnt = op->dummy.nbytes;
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u8 addr_cnt = op->addr.nbytes;
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u8 mio_width;
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unsigned int data_cnt = op->data.nbytes;
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u64 addr_offset = op->addr.val;
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/* Set the access register */
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clrsetbits_le32(&priv->regs->ar,
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GENMASK(31, 0), CA_SF_AR_ACCODE(opcode));
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if (opcode == CA_SF_AC_OP_EXTEND) { /* read_data, write_data */
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if (data_cnt > 6) {
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if (op->data.dir == SPI_MEM_DATA_IN)
|
|
mio_width = priv->rx_width;
|
|
else
|
|
mio_width = priv->tx_width;
|
|
if (_ca_sflash_mio_set(priv, mio_width))
|
|
return -1;
|
|
}
|
|
debug("%s: FLASH ACCESS reg=%#08x\n",
|
|
__func__, readl(&priv->regs->ar));
|
|
|
|
/* Use command in extend_access register */
|
|
clrsetbits_le32(&priv->regs->ear,
|
|
GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode)
|
|
| CA_SF_EAR_DUMY_CNT(dummy_cnt * 8 - 1)
|
|
| CA_SF_EAR_ADDR_CNT(addr_cnt - 1)
|
|
| CA_SF_EAR_DATA_CNT(4 - 1)
|
|
| CA_SF_EAR_DRD_CMD_EN);
|
|
debug("%s: FLASH EXT ACCESS reg=%#08x\n",
|
|
__func__, readl(&priv->regs->ear));
|
|
|
|
if (_ca_sflash_access_data(priv, op))
|
|
return -1;
|
|
} else { /* reset_op, wr_enable, wr_disable */
|
|
setbits_le32(&priv->regs->ar,
|
|
CA_SF_AR_OP(op->cmd.opcode));
|
|
debug("%s: FLASH ACCESS reg=%#08x\n",
|
|
__func__, readl(&priv->regs->ar));
|
|
|
|
if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */
|
|
/* Configure address length */
|
|
if (addr_cnt > 3) /* 4 Bytes address */
|
|
setbits_le32(&priv->regs->tr,
|
|
CA_FLASH_TR_SIZE(2));
|
|
else /* 3 Bytes address */
|
|
clrbits_le32(&priv->regs->tr,
|
|
CA_FLASH_TR_SIZE_MSK);
|
|
|
|
/* Fill address */
|
|
if (addr_cnt > 0)
|
|
clrsetbits_le32(&priv->regs->adr,
|
|
GENMASK(31, 0),
|
|
(u32)addr_offset);
|
|
}
|
|
|
|
if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
|
|
return -1;
|
|
}
|
|
/* elapse 10us before issuing any other command */
|
|
udelay(10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ca_sflash_exec_op(struct spi_slave *slave,
|
|
const struct spi_mem_op *op)
|
|
{
|
|
struct ca_sflash_priv *priv = dev_get_priv(slave->dev->parent);
|
|
u8 opcode;
|
|
|
|
debug("%s: cmd:%#02x addr.val:%#llx addr.len:%#x data.len:%#x data.dir:%#x\n",
|
|
__func__, op->cmd.opcode, op->addr.val,
|
|
op->addr.nbytes, op->data.nbytes, op->data.dir);
|
|
|
|
if (op->data.nbytes == 0 && op->addr.nbytes == 0) {
|
|
opcode = CA_SF_AC_OP;
|
|
} else if (op->data.nbytes == 0 && op->addr.nbytes > 0) {
|
|
opcode = CA_SF_AC_OP_4_ADDR;
|
|
} else if (op->data.nbytes > 0) {
|
|
opcode = CA_SF_AC_OP_EXTEND;
|
|
} else {
|
|
printf("%s: can't support cmd.opcode:(%#02x) type currently!\n",
|
|
__func__, op->cmd.opcode);
|
|
return -1;
|
|
}
|
|
|
|
return _ca_sflash_issue_cmd(priv, (struct spi_mem_op *)op, opcode);
|
|
}
|
|
|
|
static void ca_sflash_init(struct ca_sflash_priv *priv)
|
|
{
|
|
/* Set FLASH_TYPE as serial flash, value: 0x0400*/
|
|
clrsetbits_le32(&priv->regs->tr,
|
|
GENMASK(31, 0), CA_FLASH_TR_SIZE(2));
|
|
debug("%s: FLASH_TYPE reg=%#x\n",
|
|
__func__, readl(&priv->regs->tr));
|
|
|
|
/* Minimize flash timing, value: 0x07010101 */
|
|
clrsetbits_le32(&priv->regs->tmr,
|
|
GENMASK(31, 0),
|
|
CA_SF_TMR_CLK(0x07)
|
|
| CA_SF_TMR_SETUP(0x01)
|
|
| CA_SF_TMR_HOLD(0x01)
|
|
| CA_SF_TMR_IDLE(0x01));
|
|
debug("%s: FLASH_TIMING reg=%#x\n",
|
|
__func__, readl(&priv->regs->tmr));
|
|
}
|
|
|
|
static int ca_sflash_probe(struct udevice *dev)
|
|
{
|
|
struct ca_sflash_priv *priv = dev_get_priv(dev);
|
|
struct resource res;
|
|
int ret;
|
|
|
|
/* Map the registers */
|
|
ret = dev_read_resource_byname(dev, "sflash-regs", &res);
|
|
if (ret) {
|
|
dev_err(dev, "can't get regs base addresses(ret = %d)!\n", ret);
|
|
return ret;
|
|
}
|
|
priv->regs = devm_ioremap(dev, res.start, resource_size(&res));
|
|
if (IS_ERR(priv->regs))
|
|
return PTR_ERR(priv->regs);
|
|
|
|
ca_sflash_init(priv);
|
|
|
|
printf("SFLASH: Controller probed ready\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops ca_sflash_mem_ops = {
|
|
.exec_op = ca_sflash_exec_op,
|
|
};
|
|
|
|
static const struct dm_spi_ops ca_sflash_ops = {
|
|
.claim_bus = ca_sflash_claim_bus,
|
|
.release_bus = ca_sflash_release_bus,
|
|
.set_speed = ca_sflash_set_speed,
|
|
.set_mode = ca_sflash_set_mode,
|
|
.mem_ops = &ca_sflash_mem_ops,
|
|
};
|
|
|
|
static const struct udevice_id ca_sflash_ids[] = {
|
|
{.compatible = "cortina,ca-sflash"},
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(ca_sflash) = {
|
|
.name = "ca_sflash",
|
|
.id = UCLASS_SPI,
|
|
.of_match = ca_sflash_ids,
|
|
.ops = &ca_sflash_ops,
|
|
.priv_auto = sizeof(struct ca_sflash_priv),
|
|
.probe = ca_sflash_probe,
|
|
};
|