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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
159 lines
5.4 KiB
C
159 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Freescale i.MX28 OCOTP Register Definitions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __MX28_REGS_OCOTP_H__
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#define __MX28_REGS_OCOTP_H__
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#include <asm/mach-imx/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_ocotp_regs {
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mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */
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mxs_reg_32(hw_ocotp_data) /* 0x10 */
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mxs_reg_32(hw_ocotp_cust0) /* 0x20 */
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mxs_reg_32(hw_ocotp_cust1) /* 0x30 */
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mxs_reg_32(hw_ocotp_cust2) /* 0x40 */
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mxs_reg_32(hw_ocotp_cust3) /* 0x50 */
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mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */
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mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */
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mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */
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mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */
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mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
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mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
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mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
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mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
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mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
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mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
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mxs_reg_32(hw_ocotp_swcap) /* 0x100 */
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mxs_reg_32(hw_ocotp_custcap) /* 0x110 */
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mxs_reg_32(hw_ocotp_lock) /* 0x120 */
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mxs_reg_32(hw_ocotp_ops0) /* 0x130 */
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mxs_reg_32(hw_ocotp_ops1) /* 0x140 */
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mxs_reg_32(hw_ocotp_ops2) /* 0x150 */
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mxs_reg_32(hw_ocotp_ops3) /* 0x160 */
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mxs_reg_32(hw_ocotp_un0) /* 0x170 */
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mxs_reg_32(hw_ocotp_un1) /* 0x180 */
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mxs_reg_32(hw_ocotp_un2) /* 0x190 */
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mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */
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mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */
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mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */
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mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */
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mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */
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mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */
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mxs_reg_32(hw_ocotp_rom6) /* 0x200 */
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mxs_reg_32(hw_ocotp_rom7) /* 0x210 */
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mxs_reg_32(hw_ocotp_srk0) /* 0x220 */
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mxs_reg_32(hw_ocotp_srk1) /* 0x230 */
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mxs_reg_32(hw_ocotp_srk2) /* 0x240 */
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mxs_reg_32(hw_ocotp_srk3) /* 0x250 */
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mxs_reg_32(hw_ocotp_srk4) /* 0x260 */
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mxs_reg_32(hw_ocotp_srk5) /* 0x270 */
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mxs_reg_32(hw_ocotp_srk6) /* 0x280 */
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mxs_reg_32(hw_ocotp_srk7) /* 0x290 */
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mxs_reg_32(hw_ocotp_version) /* 0x2a0 */
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};
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#endif
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#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16)
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#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16
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#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16)
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#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13)
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#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
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#define OCOTP_CTRL_ERROR (1 << 9)
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#define OCOTP_CTRL_BUSY (1 << 8)
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#define OCOTP_CTRL_ADDR_MASK 0x3f
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#define OCOTP_CTRL_ADDR_OFFSET 0
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#define OCOTP_DATA_DATA_MASK 0xffffffff
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#define OCOTP_DATA_DATA_OFFSET 0
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#define OCOTP_CUST_BITS_MASK 0xffffffff
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#define OCOTP_CUST_BITS_OFFSET 0
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#define OCOTP_CRYPTO_BITS_MASK 0xffffffff
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#define OCOTP_CRYPTO_BITS_OFFSET 0
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#define OCOTP_HWCAP_BITS_MASK 0xffffffff
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#define OCOTP_HWCAP_BITS_OFFSET 0
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#define OCOTP_SWCAP_BITS_MASK 0xffffffff
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#define OCOTP_SWCAP_BITS_OFFSET 0
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#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2)
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#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1)
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#define OCOTP_LOCK_ROM7 (1 << 31)
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#define OCOTP_LOCK_ROM6 (1 << 30)
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#define OCOTP_LOCK_ROM5 (1 << 29)
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#define OCOTP_LOCK_ROM4 (1 << 28)
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#define OCOTP_LOCK_ROM3 (1 << 27)
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#define OCOTP_LOCK_ROM2 (1 << 26)
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#define OCOTP_LOCK_ROM1 (1 << 25)
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#define OCOTP_LOCK_ROM0 (1 << 24)
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#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23)
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#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22)
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#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21)
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#define OCOTP_LOCK_PIN (1 << 20)
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#define OCOTP_LOCK_OPS (1 << 19)
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#define OCOTP_LOCK_UN2 (1 << 18)
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#define OCOTP_LOCK_UN1 (1 << 17)
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#define OCOTP_LOCK_UN0 (1 << 16)
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#define OCOTP_LOCK_SRK (1 << 15)
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#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12)
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#define OCOTP_LOCK_UNALLOCATED_OFFSET 12
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#define OCOTP_LOCK_SRK_SHADOW (1 << 11)
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#define OCOTP_LOCK_ROM_SHADOW (1 << 10)
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#define OCOTP_LOCK_CUSTCAP (1 << 9)
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#define OCOTP_LOCK_HWSW (1 << 8)
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#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7)
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#define OCOTP_LOCK_HWSW_SHADOW (1 << 6)
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#define OCOTP_LOCK_CRYPTODCP (1 << 5)
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#define OCOTP_LOCK_CRYPTOKEY (1 << 4)
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#define OCOTP_LOCK_CUST3 (1 << 3)
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#define OCOTP_LOCK_CUST2 (1 << 2)
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#define OCOTP_LOCK_CUST1 (1 << 1)
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#define OCOTP_LOCK_CUST0 (1 << 0)
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#define OCOTP_OPS_BITS_MASK 0xffffffff
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#define OCOTP_OPS_BITS_OFFSET 0
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#define OCOTP_UN_BITS_MASK 0xffffffff
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#define OCOTP_UN_BITS_OFFSET 0
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#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24)
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#define OCOTP_ROM_BOOT_MODE_OFFSET 24
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#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22)
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#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22
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#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20)
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#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20
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#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14)
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#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14
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#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12)
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#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12
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#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8)
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#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8
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#define OCOTP_ROM_EMMC_USE_DDR (1 << 7)
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#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6)
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#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5)
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#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4)
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#define OCOTP_ROM_SD_MBR_BOOT (1 << 3)
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#define OCOTP_SRK_BITS_MASK 0xffffffff
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#define OCOTP_SRK_BITS_OFFSET 0
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#define OCOTP_VERSION_MAJOR_MASK (0xff << 24)
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#define OCOTP_VERSION_MAJOR_OFFSET 24
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#define OCOTP_VERSION_MINOR_MASK (0xff << 16)
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#define OCOTP_VERSION_MINOR_OFFSET 16
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#define OCOTP_VERSION_STEP_MASK 0xffff
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#define OCOTP_VERSION_STEP_OFFSET 0
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#endif /* __MX28_REGS_OCOTP_H__ */
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