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fc47cf9d05
Three boards are still not converting to use DM_I2C. They are also using the old PMIC framework. Rather than removing them, add #ifdefs to allow them to continue to build. This will give the maintainers a little more time to decide whether to convert them or not. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
626 lines
17 KiB
C
626 lines
17 KiB
C
/*
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* Copyright (C) 2011 Samsung Electronics
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* Heungjun Kim <riverful.kim@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <lcd.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mipi_dsim.h>
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#include <asm/arch/watchdog.h>
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#include <asm/arch/power.h>
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#include <power/pmic.h>
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#include <usb/dwc2_udc.h>
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#include <power/max8997_pmic.h>
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#include <power/max8997_muic.h>
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#include <power/battery.h>
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#include <power/max17042_fg.h>
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#include <libtizen.h>
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#include <usb.h>
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#include <usb_mass_storage.h>
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#include "setup.h"
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int board_rev;
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#ifdef CONFIG_REVISION_TAG
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u32 get_board_rev(void)
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{
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return board_rev;
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}
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#endif
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static void check_hw_revision(void);
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struct dwc2_plat_otg_data s5pc210_otg_data;
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int exynos_init(void)
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{
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check_hw_revision();
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printf("HW Revision:\t0x%x\n", board_rev);
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return 0;
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}
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void i2c_init_board(void)
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{
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#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
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int err;
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/* I2C_5 -> PMIC */
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err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
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if (err) {
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debug("I2C%d not configured\n", (I2C_5));
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return;
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}
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/* I2C_8 -> FG */
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gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
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gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
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gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
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gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
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#endif
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}
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#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
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static void trats_low_power_mode(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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struct exynos4_power *pwr =
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(struct exynos4_power *)samsung_get_base_power();
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/* Power down CORE1 */
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/* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
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writel(0x0, &pwr->arm_core1_configuration);
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/* Change the APLL frequency */
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/* ENABLE (1 enable) | LOCKED (1 locked) */
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/* [31] | [29] */
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/* FSEL | MDIV | PDIV | SDIV */
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/* [27] | [25:16] | [13:8] | [2:0] */
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writel(0xa0c80604, &clk->apll_con0);
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/* Change CPU0 clock divider */
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/* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
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/* [30:28] | [26:24] | [22:20] | [18:16] */
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/* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
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/* [14:12] | [10:8] | [6:4] | [2:0] */
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writel(0x00000100, &clk->div_cpu0);
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/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
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while (readl(&clk->div_stat_cpu0) & 0x1111111)
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continue;
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/* Change clock divider ratio for DMC */
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/* DMCP_RATIO | DMCD_RATIO */
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/* [22:20] | [18:16] */
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/* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
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/* [14:12] | [10:8] | [6:4] | [2:0] */
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writel(0x13113117, &clk->div_dmc0);
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/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
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while (readl(&clk->div_stat_dmc0) & 0x11111111)
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continue;
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/* Turn off unnecessary power domains */
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writel(0x0, &pwr->xxti_configuration); /* XXTI */
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writel(0x0, &pwr->cam_configuration); /* CAM */
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writel(0x0, &pwr->tv_configuration); /* TV */
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writel(0x0, &pwr->mfc_configuration); /* MFC */
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writel(0x0, &pwr->g3d_configuration); /* G3D */
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writel(0x0, &pwr->gps_configuration); /* GPS */
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writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
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/* Turn off unnecessary clocks */
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writel(0x0, &clk->gate_ip_cam); /* CAM */
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writel(0x0, &clk->gate_ip_tv); /* TV */
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writel(0x0, &clk->gate_ip_mfc); /* MFC */
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writel(0x0, &clk->gate_ip_g3d); /* G3D */
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writel(0x0, &clk->gate_ip_image); /* IMAGE */
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writel(0x0, &clk->gate_ip_gps); /* GPS */
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}
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static int pmic_init_max8997(void)
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{
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struct pmic *p = pmic_get("MAX8997_PMIC");
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int i = 0, ret = 0;
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u32 val;
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if (pmic_probe(p))
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return -1;
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/* BUCK1 VARM: 1.2V */
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val = (1200000 - 650000) / 25000;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
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val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
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/* BUCK2 VINT: 1.1V */
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val = (1100000 - 650000) / 25000;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
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val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
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/* BUCK3 G3D: 1.1V - OFF */
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ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
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val &= ~ENBUCK;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
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val = (1100000 - 750000) / 50000;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
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/* BUCK4 CAMISP: 1.2V - OFF */
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ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
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val &= ~ENBUCK;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
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val = (1200000 - 650000) / 25000;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
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/* BUCK5 VMEM: 1.2V */
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val = (1200000 - 650000) / 25000;
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for (i = 0; i < 8; i++)
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
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val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
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/* BUCK6 CAM AF: 2.8V */
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/* No Voltage Setting Register */
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/* GNSLCT 3.0X */
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val = GNSLCT;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
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/* BUCK7 VCC_SUB: 2.0V */
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val = (2000000 - 750000) / 50000;
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ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
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/* LDO1 VADC: 3.3V */
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val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
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/* LDO1 Disable active discharging */
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ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
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val &= ~LDO_ADE;
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ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
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/* LDO2 VALIVE: 1.1V */
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val = max8997_reg_ldo(1100000) | EN_LDO;
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ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
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/* LDO3 VUSB/MIPI: 1.1V */
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val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
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/* LDO4 VMIPI: 1.8V */
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val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
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/* LDO5 VHSIC: 1.2V */
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val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
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/* LDO6 VCC_1.8V_PDA: 1.8V */
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val = max8997_reg_ldo(1800000) | EN_LDO;
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ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
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/* LDO7 CAM_ISP: 1.8V */
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val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
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/* LDO8 VDAC/VUSB: 3.3V */
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val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
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/* LDO9 VCC_2.8V_PDA: 2.8V */
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val = max8997_reg_ldo(2800000) | EN_LDO;
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ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
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/* LDO10 VPLL: 1.1V */
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val = max8997_reg_ldo(1100000) | EN_LDO;
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ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
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/* LDO11 TOUCH: 2.8V */
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val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
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/* LDO12 VTCAM: 1.8V */
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val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
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/* LDO13 VCC_3.0_LCD: 3.0V */
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val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
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/* LDO14 MOTOR: 3.0V */
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val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
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/* LDO15 LED_A: 2.8V */
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val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
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/* LDO16 CAM_SENSOR: 1.8V */
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val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
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/* LDO17 VTF: 2.8V */
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val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
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/* LDO18 TOUCH_LED 3.3V */
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val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
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/* LDO21 VDDQ: 1.2V */
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val = max8997_reg_ldo(1200000) | EN_LDO;
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ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
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/* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
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val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
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ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
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ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
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if (ret) {
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puts("MAX8997 PMIC setting error!\n");
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return -1;
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}
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return 0;
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}
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#endif
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int exynos_power_init(void)
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{
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#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
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int chrg, ret;
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struct power_battery *pb;
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struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
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/*
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* For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
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* to logical I2C adapter 0
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*
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* The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
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* to logical I2C adapter 1
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*/
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ret = pmic_init(I2C_5);
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ret |= pmic_init_max8997();
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ret |= power_fg_init(I2C_9);
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ret |= power_muic_init(I2C_5);
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ret |= power_bat_init(0);
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if (ret)
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return ret;
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p_fg = pmic_get("MAX17042_FG");
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if (!p_fg) {
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puts("MAX17042_FG: Not found\n");
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return -ENODEV;
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}
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p_chrg = pmic_get("MAX8997_PMIC");
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if (!p_chrg) {
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puts("MAX8997_PMIC: Not found\n");
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return -ENODEV;
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}
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p_muic = pmic_get("MAX8997_MUIC");
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if (!p_muic) {
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puts("MAX8997_MUIC: Not found\n");
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return -ENODEV;
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}
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p_bat = pmic_get("BAT_TRATS");
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if (!p_bat) {
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puts("BAT_TRATS: Not found\n");
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return -ENODEV;
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}
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p_fg->parent = p_bat;
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p_chrg->parent = p_bat;
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p_muic->parent = p_bat;
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p_bat->low_power_mode = trats_low_power_mode;
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p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
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pb = p_bat->pbat;
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chrg = p_muic->chrg->chrg_type(p_muic);
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debug("CHARGER TYPE: %d\n", chrg);
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if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
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puts("No battery detected\n");
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return 0;
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}
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p_fg->fg->fg_battery_check(p_fg, p_bat);
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if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
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puts("CHARGE Battery !\n");
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#endif
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return 0;
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}
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static unsigned int get_hw_revision(void)
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{
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int hwrev = 0;
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char str[10];
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int i;
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/* hw_rev[3:0] == GPE1[3:0] */
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for (i = 0; i < 4; i++) {
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int pin = i + EXYNOS4_GPIO_E10;
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sprintf(str, "hw_rev%d", i);
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gpio_request(pin, str);
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gpio_cfg_pin(pin, S5P_GPIO_INPUT);
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gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
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}
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udelay(1);
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for (i = 0; i < 4; i++)
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hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
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debug("hwrev 0x%x\n", hwrev);
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return hwrev;
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}
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static void check_hw_revision(void)
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{
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int hwrev;
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hwrev = get_hw_revision();
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board_rev |= hwrev;
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}
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#ifdef CONFIG_USB_GADGET
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static int s5pc210_phy_control(int on)
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{
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#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
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int ret = 0;
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u32 val = 0;
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struct pmic *p = pmic_get("MAX8997_PMIC");
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if (!p)
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return -ENODEV;
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if (pmic_probe(p))
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return -1;
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if (on) {
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ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
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ENSAFEOUT1, LDO_ON);
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ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
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ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
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} else {
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ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
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ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
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ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
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ENSAFEOUT1, LDO_OFF);
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}
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if (ret) {
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puts("MAX8997 LDO setting error!\n");
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return -1;
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}
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#endif
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return 0;
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}
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struct dwc2_plat_otg_data s5pc210_otg_data = {
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.phy_control = s5pc210_phy_control,
|
|
.regs_phy = EXYNOS4_USBPHY_BASE,
|
|
.regs_otg = EXYNOS4_USBOTG_BASE,
|
|
.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
|
|
.usb_flags = PHY0_SLEEP,
|
|
};
|
|
|
|
int board_usb_init(int index, enum usb_init_type init)
|
|
{
|
|
debug("USB_udc_probe\n");
|
|
return dwc2_udc_probe(&s5pc210_otg_data);
|
|
}
|
|
|
|
int g_dnl_board_usb_cable_connected(void)
|
|
{
|
|
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
|
struct pmic *muic = pmic_get("MAX8997_MUIC");
|
|
if (!muic)
|
|
return 0;
|
|
|
|
return !!muic->chrg->chrg_type(muic);
|
|
#else
|
|
return false;
|
|
#endif
|
|
|
|
}
|
|
#endif
|
|
|
|
static void pmic_reset(void)
|
|
{
|
|
gpio_direction_output(EXYNOS4_GPIO_X07, 1);
|
|
gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
|
|
}
|
|
|
|
static void board_clock_init(void)
|
|
{
|
|
struct exynos4_clock *clk =
|
|
(struct exynos4_clock *)samsung_get_base_clock();
|
|
|
|
writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
|
|
writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
|
|
writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
|
|
writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
|
|
|
|
writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
|
|
writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
|
|
writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
|
|
writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
|
|
writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
|
|
writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
|
|
writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
|
|
writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
|
|
writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
|
|
writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
|
|
writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
|
|
writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
|
|
|
|
writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
|
|
writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
|
|
writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
|
|
writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
|
|
writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
|
|
writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
|
|
writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
|
|
writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
|
|
writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
|
|
writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
|
|
writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
|
|
writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
|
|
|
|
writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
|
|
writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
|
|
writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
|
|
writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
|
|
writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
|
|
writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
|
|
writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
|
|
writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
|
|
writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
|
|
writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
|
|
writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
|
|
writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
|
|
}
|
|
|
|
static void board_power_init(void)
|
|
{
|
|
struct exynos4_power *pwr =
|
|
(struct exynos4_power *)samsung_get_base_power();
|
|
|
|
/* PS HOLD */
|
|
writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
|
|
|
|
/* Set power down */
|
|
writel(0, (unsigned int)&pwr->cam_configuration);
|
|
writel(0, (unsigned int)&pwr->tv_configuration);
|
|
writel(0, (unsigned int)&pwr->mfc_configuration);
|
|
writel(0, (unsigned int)&pwr->g3d_configuration);
|
|
writel(0, (unsigned int)&pwr->lcd1_configuration);
|
|
writel(0, (unsigned int)&pwr->gps_configuration);
|
|
writel(0, (unsigned int)&pwr->gps_alive_configuration);
|
|
|
|
/* It is necessary to power down core 1 */
|
|
/* to successfully boot CPU1 in kernel */
|
|
writel(0, (unsigned int)&pwr->arm_core1_configuration);
|
|
}
|
|
|
|
static void exynos_uart_init(void)
|
|
{
|
|
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
|
|
gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
|
|
gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
|
|
gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
|
|
}
|
|
|
|
int exynos_early_init_f(void)
|
|
{
|
|
wdt_stop();
|
|
pmic_reset();
|
|
board_clock_init();
|
|
exynos_uart_init();
|
|
board_power_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void exynos_reset_lcd(void)
|
|
{
|
|
gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
|
|
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
|
|
udelay(10000);
|
|
gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
|
|
udelay(10000);
|
|
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
|
|
}
|
|
|
|
int lcd_power(void)
|
|
{
|
|
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
|
int ret = 0;
|
|
struct pmic *p = pmic_get("MAX8997_PMIC");
|
|
if (!p)
|
|
return -ENODEV;
|
|
|
|
if (pmic_probe(p))
|
|
return 0;
|
|
|
|
/* LDO15 voltage: 2.2v */
|
|
ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
|
|
/* LDO13 voltage: 3.0v */
|
|
ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
|
|
|
|
if (ret) {
|
|
puts("MAX8997 LDO setting error!\n");
|
|
return -1;
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int mipi_power(void)
|
|
{
|
|
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
|
int ret = 0;
|
|
struct pmic *p = pmic_get("MAX8997_PMIC");
|
|
if (!p)
|
|
return -ENODEV;
|
|
|
|
if (pmic_probe(p))
|
|
return 0;
|
|
|
|
/* LDO3 voltage: 1.1v */
|
|
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
|
|
/* LDO4 voltage: 1.8v */
|
|
ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
|
|
|
|
if (ret) {
|
|
puts("MAX8997 LDO setting error!\n");
|
|
return -1;
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_LCD
|
|
void exynos_lcd_misc_init(vidinfo_t *vid)
|
|
{
|
|
#ifdef CONFIG_TIZEN
|
|
get_tizen_logo_info(vid);
|
|
#endif
|
|
#ifdef CONFIG_S6E8AX0
|
|
s6e8ax0_init();
|
|
setenv("lcdinfo", "lcd=s6e8ax0");
|
|
#endif
|
|
}
|
|
#endif
|