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be0d217952
The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.
Fixes: 5ff8e54888 ("sunxi: improve throughput
in the sunxi_mmc driver")
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Generic timer implementation of get_tbclk()
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*/
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unsigned long get_tbclk(void)
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{
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unsigned long cntfrq;
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asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
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return cntfrq;
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
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/*
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* FSL erratum A-008585 says that the ARM generic timer counter "has the
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* potential to contain an erroneous value for a small number of core
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* clock cycles every time the timer value changes".
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* This sometimes leads to a consecutive counter read returning a lower
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* value than the previous one, thus reporting the time to go backwards.
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* The workaround is to read the counter twice and only return when the value
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* was the same in both reads.
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* Assumes that the CPU runs in much higher frequency than the timer.
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*/
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unsigned long timer_read_counter(void)
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{
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unsigned long cntpct;
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unsigned long temp;
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isb();
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
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while (temp != cntpct) {
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
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}
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return cntpct;
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}
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#elif CONFIG_SUNXI_A64_TIMER_ERRATUM
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/*
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* This erratum sometimes flips the lower 11 bits of the counter value
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* to all 0's or all 1's, leading to jumps forwards or backwards.
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* Backwards jumps might be interpreted all roll-overs and be treated as
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* huge jumps forward.
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* The workaround is to check whether the lower 11 bits of the counter are
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* all 0 or all 1, then discard this value and read again.
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* This occasionally discards valid values, but will catch all erroneous
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* reads and fixes the problem reliably. Also this mostly requires only a
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* single read, so does not have any significant overhead.
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* The algorithm was conceived by Samuel Holland.
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*/
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unsigned long timer_read_counter(void)
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{
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unsigned long cntpct;
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isb();
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do {
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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} while (((cntpct + 1) & GENMASK(10, 0)) <= 1);
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return cntpct;
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}
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#else
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/*
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* timer_read_counter() using the Arm Generic Timer (aka arch timer).
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*/
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unsigned long timer_read_counter(void)
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{
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unsigned long cntpct;
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isb();
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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return cntpct;
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}
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#endif
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uint64_t get_ticks(void)
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{
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unsigned long ticks = timer_read_counter();
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gd->arch.tbl = ticks;
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return ticks;
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}
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unsigned long usec2ticks(unsigned long usec)
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{
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ulong ticks;
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if (usec < 1000)
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ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
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else
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ticks = ((usec / 10) * (get_tbclk() / 100000));
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return ticks;
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}
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ulong timer_get_boot_us(void)
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{
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u64 val = get_ticks() * 1000000;
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return val / get_tbclk();
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}
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