u-boot/arch/riscv/cpu
Lukas Auer 2a23ac6107 riscv: align mtvec on a 4-byte boundary
The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:31 +08:00
..
ax25 riscv: Move do_reset() to a common place 2018-10-03 17:48:43 +08:00
qemu riscv: Move do_reset() to a common place 2018-10-03 17:48:43 +08:00
cpu.c riscv: Add a helper routine to print CPU information 2018-10-03 17:47:55 +08:00
Makefile riscv: Make start.S available for all targets 2018-10-03 17:48:14 +08:00
start.S riscv: align mtvec on a 4-byte boundary 2018-11-26 13:57:31 +08:00
u-boot.lds riscv: Make start.S available for all targets 2018-10-03 17:48:14 +08:00