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2a04e85870
Since we go through the sequence to setup the SDRC timings more than once, break this logic out into its own function and have that function call mem_ok() to make sure the memory is usable. Signed-off-by: Tom Rini <trini@ti.com>
252 lines
6.6 KiB
C
252 lines
6.6 KiB
C
/*
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* Functions related to OMAP3 SDRC.
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*
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* This file has been created after exctracting and consolidating
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* the SDRC related content from mem.c and board.c, also created
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* generic init function (mem_init).
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*
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* Copyright (C) 2004-2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2011
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
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*
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* Author :
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Original implementation by (mem.c, board.c) :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern omap3_sysinfo sysinfo;
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static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
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/*
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* is_mem_sdr -
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* - Return 1 if mem type in use is SDR
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*/
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u32 is_mem_sdr(void)
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{
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if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
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return 1;
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return 0;
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}
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/*
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* make_cs1_contiguous -
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* - When we have CS1 populated we want to have it mapped after cs0 to allow
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* command line mem=xyz use all memory with out discontinuous support
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* compiled in. We could do it in the ATAG, but there really is two banks...
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*/
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void make_cs1_contiguous(void)
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{
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u32 size, a_add_low, a_add_high;
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size = get_sdr_cs_size(CS0);
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size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
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a_add_high = (size & 3) << 8; /* set up low field */
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a_add_low = (size & 0x3C) >> 2; /* set up high field */
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writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
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}
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/*
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* get_sdr_cs_size -
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* - Get size of chip select 0/1
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*/
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u32 get_sdr_cs_size(u32 cs)
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{
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u32 size;
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/* get ram size field */
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size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
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size &= 0x3FF; /* remove unwanted bits */
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size <<= 21; /* multiply by 2 MiB to find size in MB */
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return size;
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}
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/*
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* get_sdr_cs_offset -
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* - Get offset of cs from cs0 start
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*/
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u32 get_sdr_cs_offset(u32 cs)
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{
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u32 offset;
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if (!cs)
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return 0;
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offset = readl(&sdrc_base->cs_cfg);
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offset = (offset & 15) << 27 | (offset & 0x30) << 17;
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return offset;
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}
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/*
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* write_sdrc_timings -
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* - Takes CS and associated timings and initalize SDRAM
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* - Test CS to make sure it's OK for use
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*/
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static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
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u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
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{
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/* Setup timings we got from the board. */
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writel(mcfg, &sdrc_base->cs[cs].mcfg);
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writel(ctrla, &sdrc_actim_base->ctrla);
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writel(ctrlb, &sdrc_actim_base->ctrlb);
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writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
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writel(CMD_NOP, &sdrc_base->cs[cs].manual);
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writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
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writel(mr, &sdrc_base->cs[cs].mr);
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/*
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* Test ram in this bank
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* Disable if bad or not present
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*/
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if (!mem_ok(cs))
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writel(0, &sdrc_base->cs[cs].mcfg);
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}
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/*
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* do_sdrc_init -
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* - Code called once in C-Stack only context for CS0 and with early being
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* true and a possible 2nd time depending on memory configuration from
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* stack+global context.
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*/
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void do_sdrc_init(u32 cs, u32 early)
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{
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struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
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u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
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sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
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sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
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if (early) {
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/* reset sdrc controller */
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writel(SOFTRESET, &sdrc_base->sysconfig);
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wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
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12000000);
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writel(0, &sdrc_base->sysconfig);
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/* setup sdrc to ball mux */
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writel(SDRC_SHARING, &sdrc_base->sharing);
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/* Disable Power Down of CKE because of 1 CKE on combo part */
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writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
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&sdrc_base->power);
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writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
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sdelay(0x20000);
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/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
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* to prevent this to be build in non-SPL build */
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#ifdef CONFIG_SPL_BUILD
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/*
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* If we use a SPL there is no x-loader nor config header so
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* we have to do the job ourselfs
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*/
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mcfg = V_MCFG;
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ctrla = V_ACTIMA_165;
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ctrlb = V_ACTIMB_165;
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rfr_ctrl = V_RFR_CTRL;
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mr = V_MR;
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write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
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rfr_ctrl, mr);
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#endif
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}
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/*
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* If we aren't using SPL we have been loaded by some
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* other means which may not have correctly initialized
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* both CS0 and CS1 (such as some older versions of x-loader)
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* so we may be asked now to setup CS1.
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*/
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if (cs == CS1) {
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mcfg = readl(&sdrc_base->cs[CS0].mcfg),
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rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
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ctrla = readl(&sdrc_actim_base0->ctrla),
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ctrlb = readl(&sdrc_actim_base0->ctrlb);
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mr = readl(&sdrc_base->cs[CS0].mr);
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write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
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rfr_ctrl, mr);
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}
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}
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/*
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* dram_init -
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* - Sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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/*
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* We always need to have cs_cfg point at where the second
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* bank would be, if present. Failure to do so can lead to
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* strange situations where memory isn't detected and
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* configured correctly. CS0 will already have been setup
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* at this point.
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*/
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make_cs1_contiguous();
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do_sdrc_init(CS1, NOT_EARLY);
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size1 = get_sdr_cs_size(CS1);
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gd->ram_size = size0 + size1;
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return 0;
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}
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void dram_init_banksize (void)
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{
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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size1 = get_sdr_cs_size(CS1);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
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gd->bd->bi_dram[1].size = size1;
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}
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/*
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* mem_init -
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* - Init the sdrc chip,
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* - Selects CS0 and CS1,
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*/
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void mem_init(void)
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{
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/* only init up first bank here */
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do_sdrc_init(CS0, EARLY_INIT);
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}
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