u-boot/drivers/ddr/altera/Kconfig
Simon Goldschmidt 29873c74f3 arm: socfpga: move gen5 SDR driver to DM
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.

This gets us rid of one ad-hoc call to socfpga_per_reset().

The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.

SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:16 +02:00

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config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select RAM if TARGET_SOCFPGA_GEN5
select SPL_RAM if TARGET_SOCFPGA_GEN5
help
Enable DDR SDRAM controller for the SoCFPGA devices.