u-boot/drivers/clk
Patrice Chotard 1543bf794f clk: clk_stm32f7: fix PLL clock division factor
Fix clock division factor initialization for RCC_PLLCFGR
registers.

PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17 07:44:13 -05:00
..
aspeed dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
at91 clk: at91: utmi: Set the reference clock frequency 2017-09-14 16:02:29 -04:00
exynos dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
renesas clk: rmobile: Add RPC hyperflash clock 2017-09-24 14:12:07 +09:00
rockchip rockchip: rk3399: init CPU clock when rkclk_init() 2017-11-01 11:21:32 +01:00
tegra clock: implement a driver for the Tegra CAR 2016-09-27 09:11:02 -07:00
uniphier clk: uniphier: add NAND controller clock 2017-10-15 22:32:25 +09:00
clk-uclass.c dtoc: Put phandle args in an array 2017-09-15 05:27:48 -06:00
clk_bcm6345.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_boston.c treewide: replace with error() with pr_err() 2017-10-04 11:59:44 -04:00
clk_fixed_rate.c dm: clk: fixed: Update to support livetree 2017-06-01 07:03:14 -06:00
clk_pic32.c dm: core: Replace of_offset with accessor 2017-02-08 06:12:14 -07:00
clk_sandbox.c clk: sandbox: don't check clk ID against 0 2016-06-24 17:24:35 -04:00
clk_sandbox_test.c clk: convert API to match reset/mailbox style 2016-06-19 17:05:55 -06:00
clk_stm32f7.c clk: clk_stm32f7: fix PLL clock division factor 2017-11-17 07:44:13 -05:00
clk_stm32h7.c stm32: fix STMicroelectronics copyright 2017-11-06 09:51:01 -05:00
clk_zynq.c dm: clk: Update uclass to support livetree 2017-06-01 07:03:14 -06:00
clk_zynqmp.c clk: zynqmp: Remove unused macros/variables 2017-08-02 09:11:52 +02:00
Kconfig clk: Kconfig: Add dependences of SPL_CLK 2017-09-14 13:58:22 -04:00
Makefile dm: clk: add clk driver support for stm32h7 SoCs 2017-09-22 07:40:01 -04:00