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https://github.com/AsahiLinux/u-boot
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28663622cf
Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART to s5p4418_nanopi2_defconfig. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
869 lines
23 KiB
C
869 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* Hyunseok, Jung <hsjung@nexell.co.kr>
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/clk.h>
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/*
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* clock generator macros
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*/
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#define I_PLL0_BIT (0)
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#define I_PLL1_BIT (1)
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#define I_PLL2_BIT (2)
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#define I_PLL3_BIT (3)
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#define I_EXT1_BIT (4)
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#define I_EXT2_BIT (5)
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#define I_CLKn_BIT (7)
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#define I_EXT1_BIT_FORCE (8)
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#define I_EXT2_BIT_FORCE (9)
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#define I_CLOCK_NUM 6 /* PLL0, PLL1, PLL2, PLL3, EXT1, EXT2 */
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#define I_EXECEPT_CLK (0)
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#define I_CLOCK_MASK (((1 << I_CLOCK_NUM) - 1) & ~I_EXECEPT_CLK)
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#define I_PLL0 (1 << I_PLL0_BIT)
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#define I_PLL1 (1 << I_PLL1_BIT)
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#define I_PLL2 (1 << I_PLL2_BIT)
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#define I_PLL3 (1 << I_PLL3_BIT)
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#define I_EXTCLK1 (1 << I_EXT1_BIT)
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#define I_EXTCLK2 (1 << I_EXT2_BIT)
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#define I_EXTCLK1_FORCE (1 << I_EXT1_BIT_FORCE)
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#define I_EXTCLK2_FORCE (1 << I_EXT2_BIT_FORCE)
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#define I_PLL_0_1 (I_PLL0 | I_PLL1)
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#define I_PLL_0_2 (I_PLL_0_1 | I_PLL2)
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#define I_PLL_0_3 (I_PLL_0_2 | I_PLL3)
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#define I_CLKnOUT (0)
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#define I_PCLK (1 << 16)
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#define I_BCLK (1 << 17)
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#define I_GATE_PCLK (1 << 20)
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#define I_GATE_BCLK (1 << 21)
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#define I_PCLK_MASK (I_GATE_PCLK | I_PCLK)
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#define I_BCLK_MASK (I_GATE_BCLK | I_BCLK)
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struct clk_dev_peri {
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const char *dev_name;
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void __iomem *base;
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int dev_id;
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int periph_id;
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int clk_step;
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u32 in_mask;
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u32 in_mask1;
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int div_src_0;
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int div_val_0;
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int invert_0;
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int div_src_1;
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int div_val_1;
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int invert_1;
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int in_extclk_1;
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int in_extclk_2;
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};
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struct clk_dev {
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struct clk clk;
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struct clk *link;
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const char *name;
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struct clk_dev_peri *peri;
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};
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struct clk_dev_map {
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unsigned int con_enb;
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unsigned int con_gen[4];
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};
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#define CLK_PERI_1S(name, devid, id, addr, mk)[id] = \
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{ .dev_name = name, .dev_id = devid, .periph_id = id, .clk_step = 1, \
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.base = (void *)addr, .in_mask = mk, }
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#define CLK_PERI_2S(name, devid, id, addr, mk, mk2)[id] = \
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{ .dev_name = name, .dev_id = devid, .periph_id = id, .clk_step = 2, \
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.base = (void *)addr, .in_mask = mk, .in_mask1 = mk2, }
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static const char * const clk_core[] = {
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CORECLK_NAME_PLL0, CORECLK_NAME_PLL1, CORECLK_NAME_PLL2,
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CORECLK_NAME_PLL3, CORECLK_NAME_FCLK, CORECLK_NAME_MCLK,
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CORECLK_NAME_BCLK, CORECLK_NAME_PCLK, CORECLK_NAME_HCLK,
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};
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/*
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* Section ".data" must be used because BSS is not available before relocation,
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* in board_init_f(), respectively! I.e. global variables can not be used!
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*/
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static struct clk_dev_peri clk_periphs[]
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__section(".data") = {
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CLK_PERI_1S(DEV_NAME_TIMER, 0, CLK_ID_TIMER_0,
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PHY_BASEADDR_CLKGEN14, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_TIMER, 1, CLK_ID_TIMER_1,
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PHY_BASEADDR_CLKGEN0, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_TIMER, 2, CLK_ID_TIMER_2,
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PHY_BASEADDR_CLKGEN1, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_TIMER, 3, CLK_ID_TIMER_3,
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PHY_BASEADDR_CLKGEN2, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_UART, 0, CLK_ID_UART_0,
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PHY_BASEADDR_CLKGEN22, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_UART, 1, CLK_ID_UART_1,
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PHY_BASEADDR_CLKGEN24, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_UART, 2, CLK_ID_UART_2,
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PHY_BASEADDR_CLKGEN23, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_UART, 3, CLK_ID_UART_3,
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PHY_BASEADDR_CLKGEN25, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_UART, 4, CLK_ID_UART_4,
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PHY_BASEADDR_CLKGEN26, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_UART, 5, CLK_ID_UART_5,
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PHY_BASEADDR_CLKGEN27, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_PWM, 0, CLK_ID_PWM_0,
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PHY_BASEADDR_CLKGEN13, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_PWM, 1, CLK_ID_PWM_1,
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PHY_BASEADDR_CLKGEN3, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_PWM, 2, CLK_ID_PWM_2,
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PHY_BASEADDR_CLKGEN4, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_PWM, 3, CLK_ID_PWM_3,
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PHY_BASEADDR_CLKGEN5, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_I2C, 0, CLK_ID_I2C_0,
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PHY_BASEADDR_CLKGEN6, (I_GATE_PCLK)),
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CLK_PERI_1S(DEV_NAME_I2C, 1, CLK_ID_I2C_1,
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PHY_BASEADDR_CLKGEN7, (I_GATE_PCLK)),
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CLK_PERI_1S(DEV_NAME_I2C, 2, CLK_ID_I2C_2,
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PHY_BASEADDR_CLKGEN8, (I_GATE_PCLK)),
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CLK_PERI_2S(DEV_NAME_GMAC, 0, CLK_ID_GMAC,
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PHY_BASEADDR_CLKGEN10,
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(I_PLL_0_3 | I_EXTCLK1 | I_EXTCLK1_FORCE),
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(I_CLKnOUT)),
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CLK_PERI_2S(DEV_NAME_I2S, 0, CLK_ID_I2S_0,
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PHY_BASEADDR_CLKGEN15, (I_PLL_0_3 | I_EXTCLK1),
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(I_CLKnOUT)),
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CLK_PERI_2S(DEV_NAME_I2S, 1, CLK_ID_I2S_1,
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PHY_BASEADDR_CLKGEN16, (I_PLL_0_3 | I_EXTCLK1),
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(I_CLKnOUT)),
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CLK_PERI_2S(DEV_NAME_I2S, 2, CLK_ID_I2S_2,
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PHY_BASEADDR_CLKGEN17, (I_PLL_0_3 | I_EXTCLK1),
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(I_CLKnOUT)),
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CLK_PERI_1S(DEV_NAME_SDHC, 0, CLK_ID_SDHC_0,
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PHY_BASEADDR_CLKGEN18, (I_PLL_0_2 | I_GATE_PCLK)),
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CLK_PERI_1S(DEV_NAME_SDHC, 1, CLK_ID_SDHC_1,
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PHY_BASEADDR_CLKGEN19, (I_PLL_0_2 | I_GATE_PCLK)),
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CLK_PERI_1S(DEV_NAME_SDHC, 2, CLK_ID_SDHC_2,
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PHY_BASEADDR_CLKGEN20, (I_PLL_0_2 | I_GATE_PCLK)),
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CLK_PERI_1S(DEV_NAME_SPI, 0, CLK_ID_SPI_0,
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PHY_BASEADDR_CLKGEN37, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_SPI, 1, CLK_ID_SPI_1,
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PHY_BASEADDR_CLKGEN38, (I_PLL_0_2)),
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CLK_PERI_1S(DEV_NAME_SPI, 2, CLK_ID_SPI_2,
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PHY_BASEADDR_CLKGEN39, (I_PLL_0_2)),
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};
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#define CLK_PERI_NUM ((int)ARRAY_SIZE(clk_periphs))
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#define CLK_CORE_NUM ((int)ARRAY_SIZE(clk_core))
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#define CLK_DEVS_NUM (CLK_CORE_NUM + CLK_PERI_NUM)
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#define MAX_DIVIDER ((1 << 8) - 1) /* 256, align 2 */
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static struct clk_dev st_clk_devs[CLK_DEVS_NUM]
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__section(".data");
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#define clk_dev_get(n) ((struct clk_dev *)&st_clk_devs[n])
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#define clk_container(p) (container_of(p, struct clk_dev, clk))
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/*
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* Core frequencys
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*/
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struct _core_hz_ {
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unsigned long pll[4]; /* PLL */
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unsigned long cpu_fclk, cpu_bclk; /* cpu */
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unsigned long mem_fclk, mem_dclk, mem_bclk, mem_pclk; /* ddr */
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unsigned long bus_bclk, bus_pclk; /* bus */
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#if defined(CONFIG_ARCH_S5P6818)
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unsigned long cci4_bclk, cci4_pclk; /* cci */
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#endif
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/* ip */
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unsigned long g3d_bclk;
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unsigned long coda_bclk, coda_pclk;
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#if defined(CONFIG_ARCH_S5P6818)
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unsigned long disp_bclk, disp_pclk;
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unsigned long hdmi_pclk;
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#endif
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};
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/*
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* Section ".data" must be used because BSS is not available before relocation,
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* in board_init_f(), respectively! I.e. global variables can not be used!
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*/
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/* core clock */
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static struct _core_hz_ core_hz __section(".data");
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#define CORE_HZ_SIZE (sizeof(core_hz) / 4)
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/*
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* CLKGEN HW
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*/
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static inline void clk_dev_bclk(void *base, int on)
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{
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struct clk_dev_map *reg = base;
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unsigned int val = readl(®->con_enb) & ~(0x3);
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val |= (on ? 3 : 0) & 0x3; /* always BCLK */
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writel(val, ®->con_enb);
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}
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static inline void clk_dev_pclk(void *base, int on)
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{
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struct clk_dev_map *reg = base;
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unsigned int val = 0;
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if (!on)
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return;
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val = readl(®->con_enb) & ~(1 << 3);
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val |= (1 << 3);
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writel(val, ®->con_enb);
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}
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static inline void clk_dev_rate(void *base, int step, int src, int div)
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{
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struct clk_dev_map *reg = base;
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unsigned int val = 0;
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val = readl(®->con_gen[step << 1]);
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val &= ~(0x07 << 2);
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val |= (src << 2); /* source */
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val &= ~(0xFF << 5);
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val |= (div - 1) << 5; /* divider */
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writel(val, ®->con_gen[step << 1]);
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}
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static inline void clk_dev_inv(void *base, int step, int inv)
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{
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struct clk_dev_map *reg = base;
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unsigned int val = readl(®->con_gen[step << 1]) & ~(1 << 1);
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val |= (inv << 1);
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writel(val, ®->con_gen[step << 1]);
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}
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static inline void clk_dev_enb(void *base, int on)
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{
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struct clk_dev_map *reg = base;
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unsigned int val = readl(®->con_enb) & ~(1 << 2);
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val |= ((on ? 1 : 0) << 2);
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writel(val, ®->con_enb);
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}
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/*
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* CORE FREQUENCY
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*
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* PLL0 [P,M,S] ------- | | ----- [DIV0] --- CPU-G0
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* |M| ----- [DIV1] --- BCLK/PCLK
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* PLL1 [P,M,S] ------- | | ----- [DIV2] --- DDR
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* |U| ----- [DIV3] --- 3D
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* PLL2 [P,M,S,K]-------| | ----- [DIV4] --- CODA
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* |X| ----- [DIV5] --- DISPLAY
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* PLL3 [P,M,S,K]-------| | ----- [DIV6] --- HDMI
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* | | ----- [DIV7] --- CPU-G1
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* | | ----- [DIV8] --- CCI-400(FASTBUS)
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*
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*/
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struct nx_clkpwr_registerset {
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u32 clkmodereg0; /* 0x000 : Clock Mode Register0 */
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u32 __reserved0; /* 0x004 */
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u32 pllsetreg[4]; /* 0x008 ~ 0x014 : PLL Setting Register */
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u32 __reserved1[2]; /* 0x018 ~ 0x01C */
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u32 dvoreg[9]; /* 0x020 ~ 0x040 : Divider Setting Register */
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u32 __Reserved2; /* 0x044 */
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u32 pllsetreg_sscg[6]; /* 0x048 ~ 0x05C */
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u32 __reserved3[8]; /* 0x060 ~ 0x07C */
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u8 __reserved4[0x200 - 0x80]; /* padding (0x80 ~ 0x1FF) */
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u32 gpiowakeupriseenb; /* 0x200 : GPIO Rising Edge Detect En. Reg. */
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u32 gpiowakeupfallenb; /* 0x204 : GPIO Falling Edge Detect En. Reg. */
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u32 gpiorstenb; /* 0x208 : GPIO Reset Enable Register */
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u32 gpiowakeupenb; /* 0x20C : GPIO Wakeup Source Enable */
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u32 gpiointenb; /* 0x210 : Interrupt Enable Register */
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u32 gpiointpend; /* 0x214 : Interrupt Pend Register */
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u32 resetstatus; /* 0x218 : Reset Status Register */
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u32 intenable; /* 0x21C : Interrupt Enable Register */
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u32 intpend; /* 0x220 : Interrupt Pend Register */
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u32 pwrcont; /* 0x224 : Power Control Register */
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u32 pwrmode; /* 0x228 : Power Mode Register */
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u32 __reserved5; /* 0x22C : Reserved Region */
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u32 scratch[3]; /* 0x230 ~ 0x238 : Scratch Register */
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u32 sysrstconfig; /* 0x23C : System Reset Configuration Reg. */
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u8 __reserved6[0x2A0 - 0x240]; /* padding (0x240 ~ 0x29F) */
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u32 cpupowerdownreq; /* 0x2A0 : CPU Power Down Request Register */
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u32 cpupoweronreq; /* 0x2A4 : CPU Power On Request Register */
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u32 cpuresetmode; /* 0x2A8 : CPU Reset Mode Register */
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u32 cpuwarmresetreq; /* 0x2AC : CPU Warm Reset Request Register */
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u32 __reserved7; /* 0x2B0 */
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u32 cpustatus; /* 0x2B4 : CPU Status Register */
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u8 __reserved8[0x400 - 0x2B8]; /* padding (0x2B8 ~ 0x33F) */
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};
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static struct nx_clkpwr_registerset * const clkpwr =
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(struct nx_clkpwr_registerset *)PHY_BASEADDR_CLKPWR;
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#define getquotient(v, d) ((v) / (d))
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#define DIV_CPUG0 0
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#define DIV_BUS 1
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#define DIV_MEM 2
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#define DIV_G3D 3
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#define DIV_CODA 4
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#if defined(CONFIG_ARCH_S5P6818)
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#define DIV_DISP 5
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#define DIV_HDMI 6
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#define DIV_CPUG1 7
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#define DIV_CCI4 8
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#endif
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#define DVO0 3
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#define DVO1 9
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#define DVO2 15
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#define DVO3 21
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static unsigned int pll_rate(unsigned int plln, unsigned int xtal)
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{
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unsigned int val, val1, nP, nM, nS, nK;
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unsigned int temp = 0;
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val = clkpwr->pllsetreg[plln];
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val1 = clkpwr->pllsetreg_sscg[plln];
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xtal /= 1000; /* Unit Khz */
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nP = (val >> 18) & 0x03F;
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nM = (val >> 8) & 0x3FF;
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nS = (val >> 0) & 0x0FF;
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nK = (val1 >> 16) & 0xFFFF;
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if (plln > 1 && nK) {
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temp = (unsigned int)(getquotient((getquotient((nK * 1000),
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65536) * xtal), nP) >> nS);
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}
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temp = (unsigned int)((getquotient((nM * xtal), nP) >> nS) * 1000)
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+ temp;
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return temp;
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}
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static unsigned int pll_dvo(int dvo)
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{
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unsigned int val;
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val = (clkpwr->dvoreg[dvo] & 0x7);
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return val;
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}
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static unsigned int pll_div(int dvo)
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{
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unsigned int val = clkpwr->dvoreg[dvo];
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return ((((val >> DVO3) & 0x3F) + 1) << 24) |
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((((val >> DVO2) & 0x3F) + 1) << 16) |
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((((val >> DVO1) & 0x3F) + 1) << 8) |
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((((val >> DVO0) & 0x3F) + 1) << 0);
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}
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#define PLLN_RATE(n) (pll_rate(n, CONFIG_SYS_PLLFIN)) /* 0~ 3 */
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#define CPU_FCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \
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((pll_div(n) >> 0) & 0x3F))
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#define CPU_BCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \
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((pll_div(n) >> 0) & 0x3F) / \
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((pll_div(n) >> 8) & 0x3F))
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#define MEM_FCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
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((pll_div(DIV_MEM) >> 0) & 0x3F) / \
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((pll_div(DIV_MEM) >> 8) & 0x3F))
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#define MEM_DCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
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((pll_div(DIV_MEM) >> 0) & 0x3F))
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#define MEM_BCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
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((pll_div(DIV_MEM) >> 0) & 0x3F) / \
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((pll_div(DIV_MEM) >> 8) & 0x3F) / \
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((pll_div(DIV_MEM) >> 16) & 0x3F))
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#define MEM_PCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
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((pll_div(DIV_MEM) >> 0) & 0x3F) / \
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((pll_div(DIV_MEM) >> 8) & 0x3F) / \
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((pll_div(DIV_MEM) >> 16) & 0x3F) / \
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((pll_div(DIV_MEM) >> 24) & 0x3F))
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#define BUS_BCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_BUS) >> 0) & 0x3F))
|
|
#define BUS_PCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_BUS) >> 0) & 0x3F) / \
|
|
((pll_div(DIV_BUS) >> 8) & 0x3F))
|
|
|
|
#define G3D_BCLK_RATE() (pll_rate(pll_dvo(DIV_G3D), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_G3D) >> 0) & 0x3F))
|
|
|
|
#define MPG_BCLK_RATE() (pll_rate(pll_dvo(DIV_CODA), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_CODA) >> 0) & 0x3F))
|
|
#define MPG_PCLK_RATE() (pll_rate(pll_dvo(DIV_CODA), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_CODA) >> 0) & 0x3F) / \
|
|
((pll_div(DIV_CODA) >> 8) & 0x3F))
|
|
|
|
#if defined(CONFIG_ARCH_S5P6818)
|
|
#define DISP_BCLK_RATE() (pll_rate(pll_dvo(DIV_DISP), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_DISP) >> 0) & 0x3F))
|
|
#define DISP_PCLK_RATE() (pll_rate(pll_dvo(DIV_DISP), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_DISP) >> 0) & 0x3F) / \
|
|
((pll_div(DIV_DISP) >> 8) & 0x3F))
|
|
|
|
#define HDMI_PCLK_RATE() (pll_rate(pll_dvo(DIV_HDMI), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_HDMI) >> 0) & 0x3F))
|
|
|
|
#define CCI4_BCLK_RATE() (pll_rate(pll_dvo(DIV_CCI4), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_CCI4) >> 0) & 0x3F))
|
|
#define CCI4_PCLK_RATE() (pll_rate(pll_dvo(DIV_CCI4), CONFIG_SYS_PLLFIN) / \
|
|
((pll_div(DIV_CCI4) >> 0) & 0x3F) / \
|
|
((pll_div(DIV_CCI4) >> 8) & 0x3F))
|
|
#endif
|
|
|
|
static void core_update_rate(int type)
|
|
{
|
|
switch (type) {
|
|
case 0:
|
|
core_hz.pll[0] = PLLN_RATE(0); break;
|
|
case 1:
|
|
core_hz.pll[1] = PLLN_RATE(1); break;
|
|
case 2:
|
|
core_hz.pll[2] = PLLN_RATE(2); break;
|
|
case 3:
|
|
core_hz.pll[3] = PLLN_RATE(3); break;
|
|
case 4:
|
|
core_hz.cpu_fclk = CPU_FCLK_RATE(DIV_CPUG0); break;
|
|
case 5:
|
|
core_hz.mem_fclk = MEM_FCLK_RATE(); break;
|
|
case 6:
|
|
core_hz.bus_bclk = BUS_BCLK_RATE(); break;
|
|
case 7:
|
|
core_hz.bus_pclk = BUS_PCLK_RATE(); break;
|
|
case 8:
|
|
core_hz.cpu_bclk = CPU_BCLK_RATE(DIV_CPUG0); break;
|
|
case 9:
|
|
core_hz.mem_dclk = MEM_DCLK_RATE(); break;
|
|
case 10:
|
|
core_hz.mem_bclk = MEM_BCLK_RATE(); break;
|
|
case 11:
|
|
core_hz.mem_pclk = MEM_PCLK_RATE(); break;
|
|
case 12:
|
|
core_hz.g3d_bclk = G3D_BCLK_RATE(); break;
|
|
case 13:
|
|
core_hz.coda_bclk = MPG_BCLK_RATE(); break;
|
|
case 14:
|
|
core_hz.coda_pclk = MPG_PCLK_RATE(); break;
|
|
#if defined(CONFIG_ARCH_S5P6818)
|
|
case 15:
|
|
core_hz.disp_bclk = DISP_BCLK_RATE(); break;
|
|
case 16:
|
|
core_hz.disp_pclk = DISP_PCLK_RATE(); break;
|
|
case 17:
|
|
core_hz.hdmi_pclk = HDMI_PCLK_RATE(); break;
|
|
case 18:
|
|
core_hz.cci4_bclk = CCI4_BCLK_RATE(); break;
|
|
case 19:
|
|
core_hz.cci4_pclk = CCI4_PCLK_RATE(); break;
|
|
#endif
|
|
};
|
|
}
|
|
|
|
static unsigned long core_get_rate(int type)
|
|
{
|
|
unsigned long rate = 0;
|
|
|
|
switch (type) {
|
|
case 0:
|
|
rate = core_hz.pll[0]; break;
|
|
case 1:
|
|
rate = core_hz.pll[1]; break;
|
|
case 2:
|
|
rate = core_hz.pll[2]; break;
|
|
case 3:
|
|
rate = core_hz.pll[3]; break;
|
|
case 4:
|
|
rate = core_hz.cpu_fclk; break;
|
|
case 5:
|
|
rate = core_hz.mem_fclk; break;
|
|
case 6:
|
|
rate = core_hz.bus_bclk; break;
|
|
case 7:
|
|
rate = core_hz.bus_pclk; break;
|
|
case 8:
|
|
rate = core_hz.cpu_bclk; break;
|
|
case 9:
|
|
rate = core_hz.mem_dclk; break;
|
|
case 10:
|
|
rate = core_hz.mem_bclk; break;
|
|
case 11:
|
|
rate = core_hz.mem_pclk; break;
|
|
case 12:
|
|
rate = core_hz.g3d_bclk; break;
|
|
case 13:
|
|
rate = core_hz.coda_bclk; break;
|
|
case 14:
|
|
rate = core_hz.coda_pclk; break;
|
|
#if defined(CONFIG_ARCH_S5P6818)
|
|
case 15:
|
|
rate = core_hz.disp_bclk; break;
|
|
case 16:
|
|
rate = core_hz.disp_pclk; break;
|
|
case 17:
|
|
rate = core_hz.hdmi_pclk; break;
|
|
case 18:
|
|
rate = core_hz.cci4_bclk; break;
|
|
case 19:
|
|
rate = core_hz.cci4_pclk; break;
|
|
#endif
|
|
default:
|
|
printf("unknown core clock type %d ...\n", type);
|
|
break;
|
|
};
|
|
return rate;
|
|
}
|
|
|
|
static long core_set_rate(struct clk *clk, long rate)
|
|
{
|
|
return clk->rate;
|
|
}
|
|
|
|
static void core_rate_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < CORE_HZ_SIZE; i++)
|
|
core_update_rate(i);
|
|
}
|
|
|
|
/*
|
|
* Clock Interfaces
|
|
*/
|
|
static inline long clk_divide(long rate, long request,
|
|
int align, int *divide)
|
|
{
|
|
int div = (rate / request);
|
|
int max = MAX_DIVIDER & ~(align - 1);
|
|
int adv = (div & ~(align - 1)) + align;
|
|
long ret;
|
|
|
|
if (!div) {
|
|
if (divide)
|
|
*divide = 1;
|
|
return rate;
|
|
}
|
|
|
|
if (div != 1)
|
|
div &= ~(align - 1);
|
|
|
|
if (div != adv && abs(request - rate / div) > abs(request - rate / adv))
|
|
div = adv;
|
|
|
|
div = (div > max ? max : div);
|
|
if (divide)
|
|
*divide = div;
|
|
|
|
ret = rate / div;
|
|
return ret;
|
|
}
|
|
|
|
void clk_put(struct clk *clk)
|
|
{
|
|
}
|
|
|
|
struct clk *clk_get(const char *id)
|
|
{
|
|
struct clk_dev *cdev = clk_dev_get(0);
|
|
struct clk *clk = NULL;
|
|
const char *str = NULL, *c = NULL;
|
|
int i, devid;
|
|
|
|
if (id)
|
|
str = id;
|
|
|
|
for (i = 0; i < CLK_DEVS_NUM; i++, cdev++) {
|
|
if (!cdev->name)
|
|
continue;
|
|
if (!strncmp(cdev->name, str, strlen(cdev->name))) {
|
|
c = strrchr((const char *)str, (int)'.');
|
|
if (!c || !cdev->peri)
|
|
break;
|
|
devid = dectoul(++c, NULL);
|
|
if (cdev->peri->dev_id == devid)
|
|
break;
|
|
}
|
|
}
|
|
if (i < CLK_DEVS_NUM)
|
|
clk = &cdev->clk;
|
|
else
|
|
clk = &(clk_dev_get(7))->clk; /* pclk */
|
|
|
|
return clk ? clk : ERR_PTR(-ENOENT);
|
|
}
|
|
|
|
long clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
struct clk_dev *pll = NULL, *cdev = clk_container(clk);
|
|
struct clk_dev_peri *peri = cdev->peri;
|
|
unsigned long request = rate, rate_hz = 0;
|
|
unsigned int mask;
|
|
int step, div[2] = { 0, };
|
|
int i, n, clk2 = 0;
|
|
int start_src = 0, max_src = I_CLOCK_NUM;
|
|
short s1 = 0, s2 = 0, d1 = 0, d2 = 0;
|
|
|
|
if (!peri)
|
|
return core_set_rate(clk, rate);
|
|
|
|
step = peri->clk_step;
|
|
mask = peri->in_mask;
|
|
debug("clk: %s.%d request = %ld [input=0x%x]\n", peri->dev_name,
|
|
peri->dev_id, rate, mask);
|
|
|
|
if (!(I_CLOCK_MASK & mask)) {
|
|
if (I_PCLK_MASK & mask)
|
|
return core_get_rate(CORECLK_ID_PCLK);
|
|
else if (I_BCLK_MASK & mask)
|
|
return core_get_rate(CORECLK_ID_BCLK);
|
|
else
|
|
return clk->rate;
|
|
}
|
|
|
|
next:
|
|
if (peri->in_mask & I_EXTCLK1_FORCE) {
|
|
start_src = 4; max_src = 5;
|
|
}
|
|
for (n = start_src ; max_src > n; n++) {
|
|
if (!(((mask & I_CLOCK_MASK) >> n) & 0x1))
|
|
continue;
|
|
|
|
if (n == I_EXT1_BIT) {
|
|
rate = peri->in_extclk_1;
|
|
} else if (n == I_EXT2_BIT) {
|
|
rate = peri->in_extclk_2;
|
|
} else {
|
|
pll = clk_dev_get(n);
|
|
rate = pll->clk.rate;
|
|
}
|
|
|
|
if (!rate)
|
|
continue;
|
|
|
|
for (i = 0; step > i ; i++)
|
|
rate = clk_divide(rate, request, 2, &div[i]);
|
|
|
|
if (rate_hz && (abs(rate - request) > abs(rate_hz - request)))
|
|
continue;
|
|
|
|
debug("clk: %s.%d, pll.%d[%lu] request[%ld] calc[%ld]\n",
|
|
peri->dev_name, peri->dev_id, n, pll->clk.rate,
|
|
request, rate);
|
|
|
|
if (clk2) {
|
|
s1 = -1, d1 = -1; /* not use */
|
|
s2 = n, d2 = div[0];
|
|
} else {
|
|
s1 = n, d1 = div[0];
|
|
s2 = I_CLKn_BIT, d2 = div[1];
|
|
}
|
|
rate_hz = rate;
|
|
}
|
|
|
|
/* search 2th clock from input */
|
|
if (!clk2 && abs(rate_hz - request) &&
|
|
peri->in_mask1 & ((1 << I_CLOCK_NUM) - 1)) {
|
|
clk2 = 1;
|
|
mask = peri->in_mask1;
|
|
step = 1;
|
|
goto next;
|
|
}
|
|
if (peri->in_mask & I_EXTCLK1_FORCE) {
|
|
if (s1 == 0) {
|
|
s1 = 4; s2 = 7;
|
|
d1 = 1; d2 = 1;
|
|
}
|
|
}
|
|
|
|
peri->div_src_0 = s1, peri->div_val_0 = d1;
|
|
peri->div_src_1 = s2, peri->div_val_1 = d2;
|
|
clk->rate = rate_hz;
|
|
|
|
debug("clk: %s.%d, step[%d] src[%d,%d] %ld", peri->dev_name,
|
|
peri->dev_id, peri->clk_step, peri->div_src_0, peri->div_src_1,
|
|
rate);
|
|
debug("/(div0: %d * div1: %d) = %ld, %ld diff (%ld)\n",
|
|
peri->div_val_0, peri->div_val_1, rate_hz, request,
|
|
abs(rate_hz - request));
|
|
|
|
return clk->rate;
|
|
}
|
|
|
|
unsigned long clk_get_rate(struct clk *clk)
|
|
{
|
|
struct clk_dev *cdev = clk_container(clk);
|
|
|
|
if (cdev->link)
|
|
clk = cdev->link;
|
|
return clk->rate;
|
|
}
|
|
|
|
int clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
struct clk_dev *cdev = clk_container(clk);
|
|
struct clk_dev_peri *peri = cdev->peri;
|
|
int i;
|
|
|
|
if (!peri)
|
|
return core_set_rate(clk, rate);
|
|
|
|
clk_round_rate(clk, rate);
|
|
|
|
for (i = 0; peri->clk_step > i ; i++) {
|
|
int s = (i == 0 ? peri->div_src_0 : peri->div_src_1);
|
|
int d = (i == 0 ? peri->div_val_0 : peri->div_val_1);
|
|
|
|
if (-1 == s)
|
|
continue;
|
|
|
|
clk_dev_rate(peri->base, i, s, d);
|
|
|
|
debug("clk: %s.%d (%p) set_rate [%d] src[%d] div[%d]\n",
|
|
peri->dev_name, peri->dev_id, peri->base, i, s, d);
|
|
}
|
|
|
|
return clk->rate;
|
|
}
|
|
|
|
int clk_enable(struct clk *clk)
|
|
{
|
|
struct clk_dev *cdev = clk_container(clk);
|
|
struct clk_dev_peri *peri = cdev->peri;
|
|
int i = 0, inv = 0;
|
|
|
|
if (!peri)
|
|
return 0;
|
|
|
|
debug("clk: %s.%d enable (BCLK=%s, PCLK=%s)\n", peri->dev_name,
|
|
peri->dev_id, I_GATE_BCLK & peri->in_mask ? "ON" : "PASS",
|
|
I_GATE_PCLK & peri->in_mask ? "ON" : "PASS");
|
|
|
|
if (!(I_CLOCK_MASK & peri->in_mask)) {
|
|
/* Gated BCLK/PCLK enable */
|
|
if (I_GATE_BCLK & peri->in_mask)
|
|
clk_dev_bclk(peri->base, 1);
|
|
|
|
if (I_GATE_PCLK & peri->in_mask)
|
|
clk_dev_pclk(peri->base, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* invert */
|
|
inv = peri->invert_0;
|
|
for (; peri->clk_step > i; i++, inv = peri->invert_1)
|
|
clk_dev_inv(peri->base, i, inv);
|
|
|
|
/* Gated BCLK/PCLK enable */
|
|
if (I_GATE_BCLK & peri->in_mask)
|
|
clk_dev_bclk(peri->base, 1);
|
|
|
|
if (I_GATE_PCLK & peri->in_mask)
|
|
clk_dev_pclk(peri->base, 1);
|
|
|
|
/* restore clock rate */
|
|
for (i = 0; peri->clk_step > i ; i++) {
|
|
int s = (i == 0 ? peri->div_src_0 : peri->div_src_1);
|
|
int d = (i == 0 ? peri->div_val_0 : peri->div_val_1);
|
|
|
|
if (s == -1)
|
|
continue;
|
|
clk_dev_rate(peri->base, i, s, d);
|
|
}
|
|
|
|
clk_dev_enb(peri->base, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void clk_disable(struct clk *clk)
|
|
{
|
|
struct clk_dev *cdev = clk_container(clk);
|
|
struct clk_dev_peri *peri = cdev->peri;
|
|
|
|
if (!peri)
|
|
return;
|
|
|
|
debug("clk: %s.%d disable\n", peri->dev_name, peri->dev_id);
|
|
|
|
if (!(I_CLOCK_MASK & peri->in_mask)) {
|
|
/* Gated BCLK/PCLK disable */
|
|
if (I_GATE_BCLK & peri->in_mask)
|
|
clk_dev_bclk(peri->base, 0);
|
|
|
|
if (I_GATE_PCLK & peri->in_mask)
|
|
clk_dev_pclk(peri->base, 0);
|
|
|
|
return;
|
|
}
|
|
|
|
clk_dev_rate(peri->base, 0, 7, 256); /* for power save */
|
|
clk_dev_enb(peri->base, 0);
|
|
|
|
/* Gated BCLK/PCLK disable */
|
|
if (I_GATE_BCLK & peri->in_mask)
|
|
clk_dev_bclk(peri->base, 0);
|
|
|
|
if (I_GATE_PCLK & peri->in_mask)
|
|
clk_dev_pclk(peri->base, 0);
|
|
}
|
|
|
|
/*
|
|
* Core clocks APIs
|
|
*/
|
|
void __init clk_init(void)
|
|
{
|
|
struct clk_dev *cdev = st_clk_devs;
|
|
struct clk_dev_peri *peri = clk_periphs;
|
|
struct clk *clk = NULL;
|
|
int i = 0;
|
|
|
|
memset(cdev, 0, sizeof(st_clk_devs));
|
|
core_rate_init();
|
|
|
|
for (i = 0; (CLK_CORE_NUM + CLK_PERI_NUM) > i; i++, cdev++) {
|
|
if (i < CLK_CORE_NUM) {
|
|
cdev->name = clk_core[i];
|
|
clk = &cdev->clk;
|
|
clk->rate = core_get_rate(i);
|
|
continue;
|
|
}
|
|
|
|
peri = &clk_periphs[i - CLK_CORE_NUM];
|
|
peri->base = (void *)peri->base;
|
|
|
|
cdev->peri = peri;
|
|
cdev->name = peri->dev_name;
|
|
|
|
if (!(I_CLOCK_MASK & peri->in_mask)) {
|
|
if (I_BCLK_MASK & peri->in_mask)
|
|
cdev->clk.rate = core_get_rate(CORECLK_ID_BCLK);
|
|
if (I_PCLK_MASK & peri->in_mask)
|
|
cdev->clk.rate = core_get_rate(CORECLK_ID_PCLK);
|
|
}
|
|
|
|
/* prevent uart clock disable for low step debug message */
|
|
#ifndef CONFIG_DEBUG_UART
|
|
if (peri->dev_name) {
|
|
#ifdef CONFIG_BACKLIGHT_PWM
|
|
if (!strcmp(peri->dev_name, DEV_NAME_PWM))
|
|
continue;
|
|
#endif
|
|
}
|
|
#endif
|
|
}
|
|
debug("CPU : Clock Generator= %d EA, ", CLK_DEVS_NUM);
|
|
}
|