mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
8e2e601c5f
This adds support for the ASUS C201, a RK3288-based clamshell device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters are for 4GB Samsung LPDDR3, decoded from coreboot's src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
143 lines
2.9 KiB
Text
143 lines
2.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Google Veyron Speedy Rev 1+ board device tree source
|
|
*
|
|
* Copyright 2015 Google, Inc
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "rk3288-veyron-chromebook.dtsi"
|
|
#include "cros-ec-sbs.dtsi"
|
|
#include "rk3288-veyron-speedy-u-boot.dtsi"
|
|
|
|
/ {
|
|
model = "Google Speedy";
|
|
compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
|
|
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
|
|
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
|
|
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
|
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
|
|
|
panel_regulator: panel-regulator {
|
|
compatible = "regulator-fixed";
|
|
enable-active-high;
|
|
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&lcd_enable_h>;
|
|
regulator-name = "panel_regulator";
|
|
startup-delay-us = <100000>;
|
|
vin-supply = <&vcc33_sys>;
|
|
};
|
|
|
|
vcc18_lcd: vcc18-lcd {
|
|
compatible = "regulator-fixed";
|
|
enable-active-high;
|
|
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&avdd_1v8_disp_en>;
|
|
regulator-name = "vcc18_lcd";
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
vin-supply = <&vcc18_wl>;
|
|
};
|
|
|
|
backlight_regulator: backlight-regulator {
|
|
compatible = "regulator-fixed";
|
|
enable-active-high;
|
|
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&bl_pwr_en>;
|
|
regulator-name = "backlight_regulator";
|
|
vin-supply = <&vcc33_sys>;
|
|
startup-delay-us = <15000>;
|
|
};
|
|
};
|
|
|
|
&backlight {
|
|
power-supply = <&backlight_regulator>;
|
|
};
|
|
|
|
&cpu_alert0 {
|
|
temperature = <65000>;
|
|
};
|
|
|
|
&cpu_alert1 {
|
|
temperature = <70000>;
|
|
};
|
|
|
|
&edp {
|
|
/delete-property/pinctrl-names;
|
|
/delete-property/pinctrl-0;
|
|
|
|
force-hpd;
|
|
};
|
|
|
|
&panel {
|
|
power-supply = <&panel_regulator>;
|
|
};
|
|
|
|
&rk808 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pmic_int_l>;
|
|
};
|
|
|
|
&sdmmc {
|
|
disable-wp;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
|
|
&sdmmc_bus4>;
|
|
};
|
|
|
|
&vcc_5v {
|
|
enable-active-high;
|
|
gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&drv_5v>;
|
|
};
|
|
|
|
&vcc50_hdmi {
|
|
enable-active-high;
|
|
gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&vcc50_hdmi_en>;
|
|
};
|
|
|
|
&pinctrl {
|
|
backlight {
|
|
bl_pwr_en: bl_pwr_en {
|
|
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
buck-5v {
|
|
drv_5v: drv-5v {
|
|
rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
vcc50_hdmi_en: vcc50-hdmi-en {
|
|
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
lcd {
|
|
lcd_enable_h: lcd-en {
|
|
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
avdd_1v8_disp_en: avdd-1v8-disp-en {
|
|
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pmic {
|
|
dvs_1: dvs-1 {
|
|
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
|
|
dvs_2: dvs-2 {
|
|
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
};
|