mirror of
https://github.com/AsahiLinux/u-boot
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297bb9e0fc
This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
151 lines
5.8 KiB
C
151 lines
5.8 KiB
C
/*
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* sun9i clock register definitions
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*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CLOCK_SUN9I_H
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#define _SUNXI_CLOCK_SUN9I_H
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struct sunxi_ccm_reg {
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u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
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u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
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u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
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u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
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u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
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u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
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u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
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u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
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u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
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u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */
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u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */
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u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */
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u8 reserved1[0x20]; /* 0x30 */
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u32 cpu_clk_source; /* 0x50 cpu clk source configuration */
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u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */
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u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */
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u32 gtbus_cfg; /* 0x5c gtbus clock configuration */
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u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */
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u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */
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u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */
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u8 reserved2[0x04]; /* 0x6c */
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u32 apb0_cfg; /* 0x70 apb0 clock configuration */
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u32 apb1_cfg; /* 0x74 apb1 clock configuration */
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u32 cci400_cfg; /* 0x78 cci400 clock configuration */
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u8 reserved3[0x04]; /* 0x7c */
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u32 ats_cfg; /* 0x80 ats clock configuration */
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u32 trace_cfg; /* 0x84 trace clock configuration */
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u8 reserved4[0x14]; /* 0x88 */
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u32 pll_stable_status; /* 0x9c */
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u8 reserved5[0xe0]; /* 0xa0 */
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u32 clk_output_a; /* 0x180 clk_output_a */
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u32 clk_output_b; /* 0x184 clk_output_a */
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u8 reserved6[0x278]; /* 0x188 */
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u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */
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u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
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u8 reserved7[0x08]; /* 0x408 */
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u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
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u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */
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u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */
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u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */
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u8 reserved8[0x08]; /* 0x420 */
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u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
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u32 ss_clk_cfg; /* 0x42c security system clock cfg */
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u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
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u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
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u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
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u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
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u8 reserved9[0x44]; /* 0x440 */
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u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */
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u8 reserved10[0x8]; /* 0x488 */
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u32 de_clk_cfg; /* 0x490 display engine clock configuration */
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u8 reserved11[0x04]; /* 0x494 */
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u32 mp_clk_cfg; /* 0x498 mp clock configuration */
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u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
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u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
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u8 reserved12[0x1c]; /* 0x4a4 */
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u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */
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u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
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u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
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u32 fd_clk_cfg; /* 0x4cc FD module clock */
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u32 ve_clk_cfg; /* 0x4d0 VE module clock */
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u32 avs_clk_cfg; /* 0x4d4 AVS module clock */
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u8 reserved13[0x18]; /* 0x4d8 */
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u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
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u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */
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u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */
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u8 reserved14[0x10]; /* 0x4fc */
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u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
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u8 reserved15[0x70]; /* 0x510 */
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u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
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u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
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u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
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u8 reserved16[0x04]; /* 0x58c */
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u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
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u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
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u8 reserved17[0x08]; /* 0x598 */
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u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */
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u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */
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u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */
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u8 reserved18[0x04]; /* 0x5ac */
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u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */
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u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
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};
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/* pll4_periph0_cfg */
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#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */
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#define CCM_PLL4_CTRL_N_SHIFT 8
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#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT)
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#define CCM_PLL4_CTRL_P_SHIFT 16
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#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT)
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#define CCM_PLL4_CTRL_M_SHIFT 18
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#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT)
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/* sd#_clk_cfg fields */
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#define CCM_MMC_CTRL_M(x) ((x) - 1)
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#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
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#define CCM_MMC_CTRL_N(x) ((x) << 16)
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#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
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#define CCM_MMC_CTRL_OSCM24 (0 << 24)
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#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24)
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#define CCM_MMC_CTRL_ENABLE (1 << 31)
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/* ahb_gate0 fields */
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#define AHB_GATE_OFFSET_MCTL 14
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/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
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#define AHB_GATE_OFFSET_NAND0 13
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#define AHB_GATE_OFFSET_MMC(x) 8
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/* ahb gate1 field */
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#define AHB_GATE_OFFSET_DMA 24
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/* apb1_gate fields */
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#define APB1_GATE_UART_SHIFT 16
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#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
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#define APB1_GATE_TWI_SHIFT 0
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#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
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/* ahb_reset0_cfg fields */
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#define AHB_RESET_OFFSET_MCTL 14
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/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
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#define AHB_RESET_OFFSET_MMC(x) 8
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/* apb1_reset_cfg fields */
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#define APB1_RESET_UART_SHIFT 16
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#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT)
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#define APB1_RESET_TWI_SHIFT 0
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#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT)
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#ifndef __ASSEMBLY__
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unsigned int clock_get_pll4_periph0(void);
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#endif
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#endif /* _SUNXI_CLOCK_SUN9I_H */
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