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Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RCar Gen3 USB PHY driver
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <generic-phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <power/regulator.h>
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/* USB2.0 Host registers (original offset is +0x200) */
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#define USB2_INT_ENABLE 0x000
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#define USB2_USBCTR 0x00c
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#define USB2_SPD_RSM_TIMSET 0x10c
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#define USB2_OC_TIMSET 0x110
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#define USB2_COMMCTRL 0x600
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#define USB2_OBINTSTA 0x604
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#define USB2_OBINTEN 0x608
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#define USB2_VBCTRL 0x60c
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#define USB2_LINECTRL1 0x610
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#define USB2_ADPCTRL 0x630
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/* USBCTR */
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#define USB2_USBCTR_PLL_RST BIT(1)
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/* SPD_RSM_TIMSET */
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#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
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/* OC_TIMSET */
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#define USB2_OC_TIMSET_INIT 0x000209ab
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/* COMMCTRL */
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#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
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/* LINECTRL1 */
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#define USB2_LINECTRL1_DP_RPD BIT(18)
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#define USB2_LINECTRL1_DM_RPD BIT(16)
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/* ADPCTRL */
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#define USB2_ADPCTRL_DRVVBUS BIT(4)
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struct rcar_gen3_phy {
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fdt_addr_t regs;
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struct clk clk;
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struct udevice *vbus_supply;
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};
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static int rcar_gen3_phy_phy_init(struct phy *phy)
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{
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struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
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/* Initialize USB2 part */
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writel(0, priv->regs + USB2_INT_ENABLE);
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writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
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writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);
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setbits_le32(priv->regs + USB2_LINECTRL1,
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USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
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clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
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setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
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return 0;
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}
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static int rcar_gen3_phy_phy_power_on(struct phy *phy)
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{
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struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
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int ret;
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if (priv->vbus_supply) {
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ret = regulator_set_enable(priv->vbus_supply, true);
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if (ret)
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return ret;
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}
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setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
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clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
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return 0;
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}
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static int rcar_gen3_phy_phy_power_off(struct phy *phy)
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{
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struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
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if (!priv->vbus_supply)
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return 0;
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return regulator_set_enable(priv->vbus_supply, false);
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}
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static const struct phy_ops rcar_gen3_phy_phy_ops = {
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.init = rcar_gen3_phy_phy_init,
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.power_on = rcar_gen3_phy_phy_power_on,
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.power_off = rcar_gen3_phy_phy_power_off,
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};
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static int rcar_gen3_phy_probe(struct udevice *dev)
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{
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struct rcar_gen3_phy *priv = dev_get_priv(dev);
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int ret;
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priv->regs = dev_read_addr(dev);
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if (priv->regs == FDT_ADDR_T_NONE)
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return -EINVAL;
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ret = device_get_supply_regulator(dev, "vbus-supply",
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&priv->vbus_supply);
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get PHY regulator\n");
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return ret;
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}
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/* Enable clock */
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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return 0;
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}
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static int rcar_gen3_phy_remove(struct udevice *dev)
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{
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struct rcar_gen3_phy *priv = dev_get_priv(dev);
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clk_disable(&priv->clk);
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clk_free(&priv->clk);
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return 0;
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}
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static const struct udevice_id rcar_gen3_phy_of_match[] = {
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{ .compatible = "renesas,rcar-gen3-usb2-phy", },
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{ },
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};
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U_BOOT_DRIVER(rcar_gen3_phy) = {
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.name = "rcar-gen3-phy",
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.id = UCLASS_PHY,
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.of_match = rcar_gen3_phy_of_match,
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.ops = &rcar_gen3_phy_phy_ops,
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.probe = rcar_gen3_phy_probe,
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.remove = rcar_gen3_phy_remove,
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.priv_auto_alloc_size = sizeof(struct rcar_gen3_phy),
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};
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