mirror of
https://github.com/AsahiLinux/u-boot
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ce0069ed95
If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
362 lines
9.4 KiB
C
362 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015 - 2019 MediaTek Inc.
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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* Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <mapmem.h>
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#include <asm/io.h>
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#include <dt-bindings/phy/phy.h>
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/* version V1 sub-banks offset base address */
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/* banks shared by multiple phys */
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#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
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#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
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/* u3/pcie/sata phy banks */
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#define SSUSB_SIFSLV_V1_U3PHYD 0x000
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#define SSUSB_SIFSLV_V1_U3PHYA 0x200
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#define U3P_U3_CHIP_GPIO_CTLD 0x0c
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#define P3C_REG_IP_SW_RST BIT(31)
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#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
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#define P3C_FORCE_IP_SW_RST BIT(29)
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#define U3P_U3_CHIP_GPIO_CTLE 0x10
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#define P3C_RG_SWRST_U3_PHYD BIT(25)
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#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
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#define U3P_U3_PHYA_REG0 0x000
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#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
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#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
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#define U3P_U3_PHYA_REG1 0x004
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#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
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#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
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#define U3P_U3_PHYA_DA_REG0 0x100
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#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
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#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
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#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
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#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
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#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
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#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
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#define U3P_U3_PHYA_DA_REG4 0x108
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#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
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#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
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#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
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#define U3P_U3_PHYA_DA_REG5 0x10c
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#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
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#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
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#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
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#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
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#define U3P_U3_PHYA_DA_REG6 0x110
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#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
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#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
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#define U3P_U3_PHYA_DA_REG7 0x114
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#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
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#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
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#define U3P_U3_PHYA_DA_REG20 0x13c
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#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
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#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
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#define U3P_U3_PHYA_DA_REG25 0x148
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#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
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#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
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#define U3P_U3_PHYD_RXDET1 0x128
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#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
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#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
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#define U3P_U3_PHYD_RXDET2 0x12c
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#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
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#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
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struct u3phy_banks {
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void __iomem *spllc;
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void __iomem *chip;
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void __iomem *phyd; /* include u3phyd_bank2 */
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void __iomem *phya; /* include u3phya_da */
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};
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struct mtk_phy_instance {
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void __iomem *port_base;
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const struct device_node *np;
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struct u3phy_banks u3_banks;
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/* reference clock of anolog phy */
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struct clk ref_clk;
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u32 index;
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u8 type;
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};
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struct mtk_tphy {
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void __iomem *sif_base;
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struct mtk_phy_instance **phys;
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int nphys;
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};
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static void pcie_phy_instance_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
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P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
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P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
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P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
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/* ref clk drive */
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
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P3A_RG_CLKDRV_AMP_VAL(0x4));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
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P3A_RG_CLKDRV_OFF_VAL(0x1));
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/* SSC delta -5000ppm */
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
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P3A_RG_PLL_DELTA1_PE2H,
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P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
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P3A_RG_PLL_DELTA_PE2H,
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P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
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/* change pll BW 0.6M */
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
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P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
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P3A_RG_PLL_BR_PE2H_VAL(0x1) |
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P3A_RG_PLL_IC_PE2H_VAL(0x1));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
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P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
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P3A_RG_PLL_BC_PE2H_VAL(0x3));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
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P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
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P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
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/* Tx Detect Rx Timing: 10us -> 5us */
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clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
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P3D_RG_RXDET_STB2_SET,
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P3D_RG_RXDET_STB2_SET_VAL(0x10));
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clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
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P3D_RG_RXDET_STB2_SET_P3,
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P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
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/* wait for PCIe subsys register to active */
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udelay(3000);
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}
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static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u3phy_banks *bank = &instance->u3_banks;
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clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
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P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
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clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
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P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
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}
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static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u3phy_banks *bank = &instance->u3_banks;
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setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
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P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
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setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
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P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
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}
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static void phy_v1_banks_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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switch (instance->type) {
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case PHY_TYPE_PCIE:
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u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
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u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
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u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
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u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
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break;
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default:
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return;
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}
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}
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static int mtk_phy_init(struct phy *phy)
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{
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = tphy->phys[phy->id];
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int ret;
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ret = clk_enable(&instance->ref_clk);
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if (ret)
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return ret;
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switch (instance->type) {
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case PHY_TYPE_PCIE:
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pcie_phy_instance_init(tphy, instance);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mtk_phy_power_on(struct phy *phy)
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{
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = tphy->phys[phy->id];
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pcie_phy_instance_power_on(tphy, instance);
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return 0;
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}
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static int mtk_phy_power_off(struct phy *phy)
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{
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = tphy->phys[phy->id];
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pcie_phy_instance_power_off(tphy, instance);
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return 0;
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}
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static int mtk_phy_exit(struct phy *phy)
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{
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = tphy->phys[phy->id];
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clk_disable(&instance->ref_clk);
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return 0;
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}
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static int mtk_phy_xlate(struct phy *phy,
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struct ofnode_phandle_args *args)
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{
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = NULL;
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const struct device_node *phy_np = ofnode_to_np(args->node);
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u32 index;
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if (!phy_np) {
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dev_err(phy->dev, "null pointer phy node\n");
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return -EINVAL;
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}
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if (args->args_count < 1) {
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dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
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return -EINVAL;
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}
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for (index = 0; index < tphy->nphys; index++)
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if (phy_np == tphy->phys[index]->np) {
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instance = tphy->phys[index];
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break;
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}
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if (!instance) {
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dev_err(phy->dev, "failed to find appropriate phy\n");
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return -EINVAL;
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}
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phy->id = index;
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instance->type = args->args[1];
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if (!(instance->type == PHY_TYPE_USB2 ||
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instance->type == PHY_TYPE_USB3 ||
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instance->type == PHY_TYPE_PCIE ||
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instance->type == PHY_TYPE_SATA)) {
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dev_err(phy->dev, "unsupported device type\n");
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return -EINVAL;
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}
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phy_v1_banks_init(tphy, instance);
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return 0;
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}
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static const struct phy_ops mtk_tphy_ops = {
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.init = mtk_phy_init,
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.exit = mtk_phy_exit,
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.power_on = mtk_phy_power_on,
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.power_off = mtk_phy_power_off,
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.of_xlate = mtk_phy_xlate,
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};
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static int mtk_tphy_probe(struct udevice *dev)
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{
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struct mtk_tphy *tphy = dev_get_priv(dev);
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ofnode subnode;
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int index = 0;
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dev_for_each_subnode(subnode, dev)
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tphy->nphys++;
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tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
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GFP_KERNEL);
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if (!tphy->phys)
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return -ENOMEM;
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tphy->sif_base = dev_read_addr_ptr(dev);
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if (!tphy->sif_base)
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return -ENOENT;
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dev_for_each_subnode(subnode, dev) {
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struct mtk_phy_instance *instance;
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fdt_addr_t addr;
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int err;
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instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
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if (!instance)
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return -ENOMEM;
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addr = ofnode_get_addr(subnode);
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if (addr == FDT_ADDR_T_NONE)
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return -ENOMEM;
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instance->port_base = map_sysmem(addr, 0);
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instance->index = index;
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instance->np = ofnode_to_np(subnode);
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tphy->phys[index] = instance;
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index++;
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err = clk_get_optional_nodev(subnode, "ref",
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&instance->ref_clk);
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if (err)
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return err;
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}
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return 0;
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}
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static const struct udevice_id mtk_tphy_id_table[] = {
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{ .compatible = "mediatek,generic-tphy-v1", },
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{ }
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};
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U_BOOT_DRIVER(mtk_tphy) = {
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.name = "mtk-tphy",
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.id = UCLASS_PHY,
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.of_match = mtk_tphy_id_table,
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.ops = &mtk_tphy_ops,
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.probe = mtk_tphy_probe,
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.priv_auto_alloc_size = sizeof(struct mtk_tphy),
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};
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