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https://github.com/AsahiLinux/u-boot
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abbab70363
Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
196 lines
4.4 KiB
C
196 lines
4.4 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <ipu_pixfmt.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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char *get_reset_cause(void)
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{
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u32 cause;
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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cause = readl(&src_regs->srsr);
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writel(cause, &src_regs->srsr);
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switch (cause) {
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case 0x00001:
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case 0x00011:
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return "POR";
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case 0x00004:
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return "CSU";
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case 0x00008:
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return "IPP USER";
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case 0x00010:
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return "WDOG";
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case 0x00020:
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return "JTAG HIGH-Z";
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case 0x00040:
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return "JTAG SW";
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case 0x10000:
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return "WARM BOOT";
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default:
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return "unknown reset";
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}
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}
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
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#if defined(CONFIG_MX53)
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#define MEMCTL_BASE ESDCTL_BASE_ADDR;
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#else
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#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
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#endif
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static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
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static const unsigned char bank_lookup[] = {3, 2};
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struct esd_mmdc_regs {
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uint32_t ctl;
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uint32_t pdc;
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uint32_t otc;
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uint32_t cfg0;
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uint32_t cfg1;
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uint32_t cfg2;
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uint32_t misc;
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uint32_t scr;
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uint32_t ref;
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uint32_t rsvd1;
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uint32_t rsvd2;
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uint32_t rwd;
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uint32_t or;
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uint32_t mrr;
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uint32_t cfg3lp;
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uint32_t mr4;
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};
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#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
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#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
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#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
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#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
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#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
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unsigned imx_ddr_size(void)
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{
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struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
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unsigned ctl = readl(&mem->ctl);
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unsigned misc = readl(&mem->misc);
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int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
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bits += ESD_MMDC_CTL_GET_ROW(ctl);
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bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
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bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
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bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
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bits += ESD_MMDC_CTL_GET_CS1(ctl);
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return 1 << bits;
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}
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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const char *get_imx_type(u32 imxtype)
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{
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switch (imxtype) {
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case MXC_CPU_MX6Q:
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return "6Q"; /* Quad-core version of the mx6 */
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case MXC_CPU_MX6DL:
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return "6DL"; /* Dual Lite version of the mx6 */
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case MXC_CPU_MX6SOLO:
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return "6SOLO"; /* Solo version of the mx6 */
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case MXC_CPU_MX6SL:
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return "6SL"; /* Solo-Lite version of the mx6 */
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case MXC_CPU_MX51:
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return "51";
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case MXC_CPU_MX53:
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return "53";
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default:
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return "??";
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}
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}
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int print_cpuinfo(void)
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{
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u32 cpurev;
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cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
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get_imx_type((cpurev & 0xFF000) >> 12),
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(cpurev & 0x000F0) >> 4,
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(cpurev & 0x0000F) >> 0,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("Reset cause: %s\n", get_reset_cause());
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_FEC_MXC)
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rc = fecmxc_initialize(bis);
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#endif
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return rc;
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}
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#ifdef CONFIG_FSL_ESDHC
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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u32 get_ahb_clk(void)
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{
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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u32 reg, ahb_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
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ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
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return get_periph_clk() / (ahb_podf + 1);
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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void arch_preboot_os(void)
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{
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/* disable video before launching O/S */
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ipuv3_fb_shutdown();
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}
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#endif
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