mirror of
https://github.com/AsahiLinux/u-boot
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0016e62813
Enable DM_SERIAL for both U_Boot and the SPL. The uart4 and its pinmux are already marked with u-boot,dm-spl but we need to move the call to preloader_console_init() after spl_init() to avoid a board hang as dm can't be used until after spl_init(). Remove the manual config of the UART pinmux now that it is no longer needed. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
90 lines
1.6 KiB
C
90 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Collabora Ltd.
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*
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*/
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#include <hang.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mn_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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int ret;
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debug("Normal Boot\n");
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0)
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puts("Failed to find clock node. Check device tree\n");
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}
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static const iomux_v3_cfg_t wdog_pads[] = {
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IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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init_uart_clk(3);
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if (IS_ENABLED(CONFIG_NAND_MXS)) {
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init_nand_clk();
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}
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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arch_cpu_init();
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board_early_init_f();
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timer_init();
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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