u-boot/arch/arm/include/asm/arch-mx5
Chris Kuethe 1005ccda97 patch - arm - define SYS_CACHELINE_SIZE for mx5
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards

Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too

Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Matthew Starr <mstarr@hedonline.com>
Cc: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-06-09 12:00:42 +02:00
..
clock.h arm: mx5: Add fuse supply enable in fsl_iim 2014-01-03 15:44:06 +01:00
crm_regs.h ARM: mx5: Fix CHSCCDR name 2014-08-20 12:19:20 +02:00
gpio.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
imx-regs.h patch - arm - define SYS_CACHELINE_SIZE for mx5 2015-06-09 12:00:42 +02:00
iomux-mx51.h imx: iomux-v3: Add missing definitions to iomux-mx51.h 2013-05-05 17:55:04 +02:00
iomux-mx53.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
sys_proto.h mx5: fix get_reset_cause 2015-03-05 10:29:27 +01:00