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https://github.com/AsahiLinux/u-boot
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9729dc9565
Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
288 lines
9.8 KiB
C
288 lines
9.8 KiB
C
/*
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* Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
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* Copyright (c) 2005 MontaVista Software
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* Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _EHCI_CI_H
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#define _EHCI_CI_H
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#include <asm/processor.h>
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#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
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/* Global offsets */
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#define FSL_SKIP_PCI 0x100
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3 << 30)
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#define PORT_PTS_UTMI (0 << 30)
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#define PORT_PTS_ULPI (2 << 30)
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#define PORT_PTS_SERIAL (3 << 30)
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#define PORT_PTS_PTW (1 << 28)
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#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
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#define PORT_PTS_PHCD (1 << 23)
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#define PORT_PP (1 << 12)
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#define PORT_PR (1 << 8)
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/* USBMODE Register bits */
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#define CM_IDLE (0 << 0)
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#define CM_RESERVED (1 << 0)
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#define CM_DEVICE (2 << 0)
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#define CM_HOST (3 << 0)
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#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
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#define USBMODE_RESERVED_2 (0 << 2)
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#define SLOM (1 << 3)
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#define SDIS (1 << 4)
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/* CONTROL Register bits */
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#define ULPI_INT_EN (1 << 0)
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#define WU_INT_EN (1 << 1)
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#define USB_EN (1 << 2)
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#define LSF_EN (1 << 3)
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#define KEEP_OTG_ON (1 << 4)
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#define OTG_PORT (1 << 5)
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#define REFSEL_12MHZ (0 << 6)
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#define REFSEL_16MHZ (1 << 6)
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#define REFSEL_48MHZ (2 << 6)
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#define PLL_RESET (1 << 8)
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#define UTMI_PHY_EN (1 << 9)
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#define PHY_CLK_SEL_UTMI (0 << 10)
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#define PHY_CLK_SEL_ULPI (1 << 10)
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#define CLKIN_SEL_USB_CLK (0 << 11)
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#define CLKIN_SEL_USB_CLK2 (1 << 11)
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#define CLKIN_SEL_SYS_CLK (2 << 11)
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#define CLKIN_SEL_SYS_CLK2 (3 << 11)
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#define RESERVED_18 (0 << 13)
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#define RESERVED_17 (0 << 14)
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#define RESERVED_16 (0 << 15)
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#define WU_INT (1 << 16)
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#define PHY_CLK_VALID (1 << 17)
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#define FSL_SOC_USB_PORTSC2 0x188
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/* OTG Status Control Register bits */
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#define FSL_SOC_USB_OTGSC 0x1a4
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#define CTRL_VBUS_DISCHARGE (0x1<<0)
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#define CTRL_VBUS_CHARGE (0x1<<1)
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#define CTRL_OTG_TERMINATION (0x1<<3)
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#define CTRL_DATA_PULSING (0x1<<4)
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#define CTRL_ID_PULL_EN (0x1<<5)
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#define HA_DATA_PULSE (0x1<<6)
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#define HA_BA (0x1<<7)
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#define STS_USB_ID (0x1<<8)
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#define STS_A_VBUS_VALID (0x1<<9)
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#define STS_A_SESSION_VALID (0x1<<10)
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#define STS_B_SESSION_VALID (0x1<<11)
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#define STS_B_SESSION_END (0x1<<12)
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#define STS_1MS_TOGGLE (0x1<<13)
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#define STS_DATA_PULSING (0x1<<14)
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#define INTSTS_USB_ID (0x1<<16)
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#define INTSTS_A_VBUS_VALID (0x1<<17)
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#define INTSTS_A_SESSION_VALID (0x1<<18)
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#define INTSTS_B_SESSION_VALID (0x1<<19)
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#define INTSTS_B_SESSION_END (0x1<<20)
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#define INTSTS_1MS (0x1<<21)
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#define INTSTS_DATA_PULSING (0x1<<22)
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#define INTR_USB_ID_EN (0x1<<24)
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#define INTR_A_VBUS_VALID_EN (0x1<<25)
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#define INTR_A_SESSION_VALID_EN (0x1<<26)
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#define INTR_B_SESSION_VALID_EN (0x1<<27)
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#define INTR_B_SESSION_END_EN (0x1<<28)
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#define INTR_1MS_TIMER_EN (0x1<<29)
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#define INTR_DATA_PULSING_EN (0x1<<30)
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#define INTSTS_MASK (0x00ff0000)
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#define INTERRUPT_ENABLE_BITS_MASK \
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(INTR_USB_ID_EN | \
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INTR_1MS_TIMER_EN | \
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INTR_A_VBUS_VALID_EN | \
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INTR_A_SESSION_VALID_EN | \
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INTR_B_SESSION_VALID_EN | \
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INTR_B_SESSION_END_EN | \
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INTR_DATA_PULSING_EN)
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#define INTERRUPT_STATUS_BITS_MASK \
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(INTSTS_USB_ID | \
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INTR_1MS_TIMER_EN | \
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INTSTS_A_VBUS_VALID | \
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INTSTS_A_SESSION_VALID | \
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INTSTS_B_SESSION_VALID | \
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INTSTS_B_SESSION_END | \
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INTSTS_DATA_PULSING)
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#define FSL_SOC_USB_USBMODE 0x1a8
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#define USBGENCTRL 0x200 /* NOTE: big endian */
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#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
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#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
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#define GC_PPP (1 << 3) /* Port Power Polarity */
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#define GC_PFP (1 << 2) /* Power Fault Polarity */
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#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
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#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
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#define ISIPHYCTRL 0x204 /* NOTE: big endian */
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#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
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#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
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#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
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#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
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#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define SNOOP_SIZE_2GB 0x1e
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/* System Clock Control Register */
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#define MPC83XX_SCCR_USB_MASK 0x00f00000
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#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
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#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
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#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
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#if defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
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#if defined(CONFIG_MPC834x)
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#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
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#else
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#define CONFIG_SYS_FSL_USB2_ADDR 0
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#endif
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#elif defined(CONFIG_MPC85xx)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
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#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
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#elif defined(CONFIG_MPC512X)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
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#define CONFIG_SYS_FSL_USB2_ADDR 0
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#elif defined(CONFIG_LS102XA)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_USB2_ADDR 0
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#endif
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/*
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* Increasing TX FIFO threshold value from 2 to 4 decreases
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* data burst rate with which data packets are posted from the TX
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* latency FIFO to compensate for latencies in DDR pipeline during DMA
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*/
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#define TXFIFOTHRESH 4
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/*
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* USB Registers
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*/
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struct usb_ehci {
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u32 id; /* 0x000 - Identification register */
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u32 hwgeneral; /* 0x004 - General hardware parameters */
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u32 hwhost; /* 0x008 - Host hardware parameters */
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u32 hwdevice; /* 0x00C - Device hardware parameters */
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u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
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u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
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u8 res1[0x68];
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u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
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u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
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u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
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u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
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u32 sbuscfg; /* 0x090 - System Bus Interface Control */
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u32 sbusstatus; /* 0x094 - System Bus Interface Status */
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u32 sbusmode; /* 0x098 - System Bus Interface Mode */
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u32 genconfig; /* 0x09C - USB Core Configuration */
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u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
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u8 res2[0x5c];
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u8 caplength; /* 0x100 - Capability Register Length */
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u8 res3[0x1];
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u16 hciversion; /* 0x102 - Host Interface Version */
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u32 hcsparams; /* 0x104 - Host Structural Parameters */
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u32 hccparams; /* 0x108 - Host Capability Parameters */
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u8 res4[0x14];
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u32 dciversion; /* 0x120 - Device Interface Version */
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u32 dciparams; /* 0x124 - Device Controller Params */
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u8 res5[0x18];
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u32 usbcmd; /* 0x140 - USB Command */
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u32 usbsts; /* 0x144 - USB Status */
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u32 usbintr; /* 0x148 - USB Interrupt Enable */
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u32 frindex; /* 0x14C - USB Frame Index */
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u8 res6[0x4];
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u32 perlistbase; /* 0x154 - Periodic List Base
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- USB Device Address */
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u32 ep_list_addr; /* 0x158 - Next Asynchronous List
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- End Point Address */
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u8 res7[0x4];
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u32 burstsize; /* 0x160 - Programmable Burst Size */
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#define FSL_EHCI_TXPBURST(X) ((X) << 8)
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#define FSL_EHCI_RXPBURST(X) (X)
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u32 txfilltuning; /* 0x164 - Host TT Transmit
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pre-buffer packet tuning */
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u8 res8[0x8];
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u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
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u8 res9[0xc];
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u32 config_flag; /* 0x180 - Configured Flag Register */
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u32 portsc; /* 0x184 - Port status/control */
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u8 res10[0x1C];
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u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
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u32 usbmode; /* 0x1a8 - USB Device Mode */
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u32 epsetupstat; /* 0x1ac - End Point Setup Status */
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u32 epprime; /* 0x1b0 - End Point Init Status */
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u32 epflush; /* 0x1b4 - End Point De-initlialize */
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u32 epstatus; /* 0x1b8 - End Point Status */
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u32 epcomplete; /* 0x1bc - End Point Complete */
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u32 epctrl0; /* 0x1c0 - End Point Control 0 */
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u32 epctrl1; /* 0x1c4 - End Point Control 1 */
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u32 epctrl2; /* 0x1c8 - End Point Control 2 */
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u32 epctrl3; /* 0x1cc - End Point Control 3 */
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u32 epctrl4; /* 0x1d0 - End Point Control 4 */
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u32 epctrl5; /* 0x1d4 - End Point Control 5 */
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u8 res11[0x28];
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u32 usbgenctrl; /* 0x200 - USB General Control */
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u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
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u8 res12[0x1F8];
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u32 snoop1; /* 0x400 - Snoop 1 */
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u32 snoop2; /* 0x404 - Snoop 2 */
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u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
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u32 prictrl; /* 0x40c - Priority Control */
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u32 sictrl; /* 0x410 - System Interface Control */
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u8 res13[0xEC];
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u32 control; /* 0x500 - Control */
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u8 res14[0xafc];
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};
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/*
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* For MXC SOCs
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*/
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/* values for portsc field */
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#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
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#define MXC_EHCI_FORCE_FS (1 << 24)
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#define MXC_EHCI_UTMI_8BIT (0 << 28)
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#define MXC_EHCI_UTMI_16BIT (1 << 28)
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#define MXC_EHCI_SERIAL (1 << 29)
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#define MXC_EHCI_MODE_UTMI (0 << 30)
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#define MXC_EHCI_MODE_PHILIPS (1 << 30)
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#define MXC_EHCI_MODE_ULPI (2 << 30)
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#define MXC_EHCI_MODE_SERIAL (3 << 30)
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/* values for flags field */
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#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
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#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
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#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
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#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
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#define MXC_EHCI_INTERFACE_MASK (0xf)
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#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
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#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
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#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
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#define MXC_EHCI_TTL_ENABLED (1 << 8)
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#define MXC_EHCI_INTERNAL_PHY (1 << 9)
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#define MXC_EHCI_IPPUE_DOWN (1 << 10)
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#define MXC_EHCI_IPPUE_UP (1 << 11)
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int usb_phy_mode(int port);
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/* Board-specific initialization */
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int board_ehci_hcd_init(int port);
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int board_usb_phy_mode(int port);
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#endif /* _EHCI_CI_H */
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