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https://github.com/AsahiLinux/u-boot
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28f40d4a4d
The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
136 lines
3.7 KiB
Text
136 lines
3.7 KiB
Text
U-Boot for UniPhier SoC family
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==============================
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Tested toolchains
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-----------------
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(a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-)
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If you are building U-Boot on Ubuntu, its standard package is recommended.
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You can install it as follows:
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$ sudo apt-get install gcc-arm-linux-gnueabi-
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(b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-)
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You can download pre-built toolchains from:
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http://www.linaro.org/downloads/
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(c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-)
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You can download pre-built toolchains from:
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ftp://www.kernel.org/pub/tools/crosstool/files/bin/
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Compile the source
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------------------
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PH1-sLD3:
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$ make ph1_sld3_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabi-
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PH1-LD4:
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$ make ph1_ld4_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabi-
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PH1-Pro4:
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$ make ph1_pro4_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabi-
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PH1-sLD8:
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$ make ph1_sld8_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabi-
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PH1-Pro5:
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$ make ph1_pro5_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabi-
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You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
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to use your favorite compiler.
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Burn U-Boot images to NAND
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--------------------------
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Write two files to the NAND device as follows:
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- spl/u-boot-spl-dtb.bin at the offset address 0x00000000
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- u-boot-dtb.img at the offset address 0x00010000
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If a TFTP server is available, the images can be easily updated.
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Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public
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directory, and then run the following command at the U-Boot command line:
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=> run nandupdate
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UniPhier specific commands
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--------------------------
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- pinmon (enabled by CONFIG_CMD_PINMON)
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shows the boot mode pins that has been latched at the power-on reset
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- ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
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shows the DDR PHY parameters set by the PHY training
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Supported devices
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-----------------
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- UART (on-chip)
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- NAND
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- USB 2.0 (EHCI)
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- USB 3.0 (xHCI)
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- LAN (on-board SMSC9118)
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- I2C
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- EEPROM (connected to the on-board I2C bus)
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- Support card (SRAM, NOR flash, some peripherals)
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Micro Support Card
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------------------
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The recommended bit switch settings are as follows:
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SW2 OFF(1)/ON(0) Description
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------------------------------------------
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bit 1 <---- BKSZ[0]
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bit 2 ----> BKSZ[1]
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bit 3 <---- SoC Bus Width 16/32
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bit 4 <---- SERIAL_SEL[0]
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bit 5 ----> SERIAL_SEL[1]
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bit 6 ----> BOOTSWAP_EN
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bit 7 <---- CS1/CS5
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bit 8 <---- SOC_SERIAL_DISABLE
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SW8 OFF(1)/ON(0) Description
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------------------------------------------
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bit 1 ----> CS1_SPLIT
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bit 2 <---- CASE9_ON
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bit 3 <---- CASE10_ON
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bit 4 Don't Care Reserve
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bit 5 Don't Care Reserve
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bit 6 Don't Care Reserve
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bit 7 ----> BURST_EN
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bit 8 ----> FLASHBUS32_16
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The BKSZ[1:0] specifies the address range of memory slot and peripherals
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as follows:
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BKSZ Description RAM slot Peripherals
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--------------------------------------------------------------------
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0b00 15MB RAM / 1MB Peri 00000000-0effffff 0f000000-0fffffff
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0b01 31MB RAM / 1MB Peri 00000000-1effffff 1f000000-1fffffff
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0b10 64MB RAM / 1MB Peri 00000000-3effffff 3f000000-3fffffff
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0b11 127MB RAM / 1MB Peri 00000000-7effffff 7f000000-7fffffff
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Set BSKZ[1:0] to 0b01 for U-Boot.
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This mode is the most handy because EA[24] is always supported by the save pin
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mode of the system bus. On the other hand, EA[25] is not supported for some
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newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
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--
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Masahiro Yamada <yamada.masahiro@socionext.com>
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Aug. 2015
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