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2372e14f19
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/*
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* Copyright (C) 2012
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* Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CADENCE_QSPI_H__
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#define __CADENCE_QSPI_H__
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#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
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#define CQSPI_NO_DECODER_MAX_CS 4
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#define CQSPI_DECODER_MAX_CS 16
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#define CQSPI_READ_CAPTURE_MAX_DELAY 16
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struct cadence_spi_platdata {
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unsigned int max_hz;
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void *regbase;
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void *ahbbase;
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u32 page_size;
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u32 block_size;
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u32 tshsl_ns;
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u32 tsd2d_ns;
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u32 tchsh_ns;
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u32 tslch_ns;
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u32 sram_size;
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};
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struct cadence_spi_priv {
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void *regbase;
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void *ahbbase;
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size_t cmd_len;
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u8 cmd_buf[32];
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size_t data_len;
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int qspi_is_init;
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unsigned int qspi_calibrated_hz;
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unsigned int qspi_calibrated_cs;
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unsigned int previous_hz;
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};
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/* Functions call declaration */
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void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
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void cadence_qspi_apb_controller_enable(void *reg_base_addr);
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void cadence_qspi_apb_controller_disable(void *reg_base_addr);
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int cadence_qspi_apb_command_read(void *reg_base_addr,
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unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
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int cadence_qspi_apb_command_write(void *reg_base_addr,
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unsigned int cmdlen, const u8 *cmdbuf,
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unsigned int txlen, const u8 *txbuf);
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int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
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unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
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int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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unsigned int rxlen, u8 *rxbuf);
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int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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unsigned int cmdlen, const u8 *cmdbuf);
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int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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unsigned int txlen, const u8 *txbuf);
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void cadence_qspi_apb_chipselect(void *reg_base,
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unsigned int chip_select, unsigned int decoder_enable);
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void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
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unsigned int clk_pol, unsigned int clk_pha);
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void cadence_qspi_apb_config_baudrate_div(void *reg_base,
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unsigned int ref_clk_hz, unsigned int sclk_hz);
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void cadence_qspi_apb_delay(void *reg_base,
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unsigned int ref_clk, unsigned int sclk_hz,
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unsigned int tshsl_ns, unsigned int tsd2d_ns,
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unsigned int tchsh_ns, unsigned int tslch_ns);
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void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
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void cadence_qspi_apb_readdata_capture(void *reg_base,
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unsigned int bypass, unsigned int delay);
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#endif /* __CADENCE_QSPI_H__ */
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