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https://github.com/AsahiLinux/u-boot
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54e1aa236f
Add support for the Variscite VAR-SOM-IMX93 evaluation kit. The SoM consists of an NXP iMX93 dual A55 CPU. The SoM is mounted on a Variscite Symphony SBC. Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
126 lines
2.8 KiB
C
126 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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* Copyright 2023 Variscite Ltd.
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*/
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#include <env.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/global_data.h>
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#include <asm/arch-imx9/ccm_regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx9/imx93_pins.h>
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#include <asm/arch/clock.h>
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#include <power/pmic.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include "../common/imx9_eeprom.h"
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#include "../common/eth.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CARRIER_EEPROM_ADDR 0x54
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#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static const iomux_v3_cfg_t uart_pads[] = {
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MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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init_uart_clk(LPUART1_CLK_ROOT);
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return 0;
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}
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int board_phys_sdram_size(phys_size_t *size)
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{
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struct var_eeprom *ep = VAR_EEPROM_DATA;
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var_eeprom_get_dram_size(ep, size);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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static int setup_eqos(void)
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{
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struct blk_ctrl_wakeupmix_regs *bctrl =
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(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&bctrl->eqos_gpr,
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BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
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BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
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return set_clk_eqos(ENET_125MHZ);
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}
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int board_init(void)
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{
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set_clk_enet(ENET_125MHZ);
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if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
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setup_eqos();
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return 0;
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}
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#define SDRAM_SIZE_STR_LEN 5
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int board_late_init(void)
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{
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int ret;
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struct var_eeprom *ep = VAR_EEPROM_DATA;
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char sdram_size_str[SDRAM_SIZE_STR_LEN];
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struct var_carrier_eeprom carrier_eeprom;
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char carrier_rev[CARRIER_REV_LEN] = {0};
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char som_rev[CARRIER_REV_LEN] = {0};
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var_setup_mac(ep);
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var_eeprom_print_prod_info(ep);
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/* SDRAM ENV */
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snprintf(sdram_size_str, SDRAM_SIZE_STR_LEN, "%d",
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(int)(gd->ram_size / 1024 / 1024));
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env_set("sdram_size", sdram_size_str);
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/* Carrier Board ENV */
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ret = var_carrier_eeprom_read(VAR_CARRIER_EEPROM_I2C_NAME,
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CARRIER_EEPROM_ADDR, &carrier_eeprom);
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if (!ret) {
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var_carrier_eeprom_get_revision(&carrier_eeprom, carrier_rev,
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sizeof(carrier_rev));
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env_set("carrier_rev", carrier_rev);
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}
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/* SoM Rev ENV */
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snprintf(som_rev, CARRIER_REV_LEN, "som_rev1%d", ep->somrev);
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env_set("som_rev", som_rev);
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if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
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board_late_mmc_env_init();
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env_set("sec_boot", "no");
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if (IS_ENABLED(CONFIG_AHAB_BOOT))
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env_set("sec_boot", "yes");
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if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
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env_set("board_name", "VAR-SOM-MX93");
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return 0;
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}
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