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Import DRAM timings generated by the DDR tool 3.31 which introduce assorted tweaks to the DRAM controller settings. Furthermore, enable DBI to improve noise resilience of the DRAM bus by reducing the number of bit changes on the bus. Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors reported by EDAC . It is not entirely clear why the slightly faster setting does produce sporadic correctable errors, while this one does not, but this could be related to simpler PLL setting at 3600 MTps. Enable inline ECC which is necessary to detect ECC errors and collect statistics by the EDAC driver in Linux. This reduces the DRAM size by 64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size becomes 1.8 GiB. Signed-off-by: Marek Vasut <marex@denx.de>
20 lines
531 B
C
20 lines
531 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2022 Marek Vasut <marex@denx.de>
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*/
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#ifndef __LPDDR4_TIMING_H__
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#define __LPDDR4_TIMING_H__
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extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
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extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
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typedef void (*scrub_func_t)(void);
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extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
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extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
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u8 dh_get_memcfg(void);
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#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
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#endif /* __LPDDR4_TIMING_H__ */
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