mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 05:23:34 +00:00
b94a3c2ebe
Sync location with mainline kernel.
Added by Linux kernel commit 75926f07baae
("arm64: dts: zynqmp: Add missing gpio-controller to ps gpio").
Fixes: 0b33e0b156 ("arm64: zynqmp: Add missing gpio property to dtsi")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
1079 lines
28 KiB
Text
1079 lines
28 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP
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*
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* (C) Copyright 2014 - 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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/ {
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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operating-points-v2 = <&cpu_opp_table>;
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reg = <0x0>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x40000000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <600>;
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min-residency-us = <10000>;
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};
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};
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};
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cpu_opp_table: cpu-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <1199999988>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <599999994>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <399999996>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <299999997>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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};
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zynqmp_ipi {
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u-boot,dm-pre-reloc;
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compatible = "xlnx,zynqmp-ipi-mailbox";
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interrupt-parent = <&gic>;
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interrupts = <0 35 4>;
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xlnx,ipi-id = <0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ipi_mailbox_pmu1: mailbox@ff990400 {
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u-boot,dm-pre-reloc;
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reg = <0x0 0xff9905c0 0x0 0x20>,
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<0x0 0xff9905e0 0x0 0x20>,
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<0x0 0xff990e80 0x0 0x20>,
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<0x0 0xff990ea0 0x0 0x20>;
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reg-names = "local_request_region", "local_response_region",
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"remote_request_region", "remote_response_region";
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#mbox-cells = <1>;
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xlnx,ipi-id = <4>;
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};
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <0 143 4>,
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<0 144 4>,
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<0 145 4>,
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<0 146 4>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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#power-domain-cells = <0x1>;
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u-boot,dm-pre-reloc;
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zynqmp_power: zynqmp-power {
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u-boot,dm-pre-reloc;
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compatible = "xlnx,zynqmp-power";
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interrupt-parent = <&gic>;
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interrupts = <0 35 4>;
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mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
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mbox-names = "tx", "rx";
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};
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zynqmp_reset: reset-controller {
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compatible = "xlnx,zynqmp-reset";
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#reset-cells = <1>;
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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edac {
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compatible = "arm,cortex-a53-edac";
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};
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fpga_full: fpga-full {
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compatible = "fpga-region";
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fpga-mgr = <&pcap>;
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#address-cells = <2>;
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#size-cells = <2>;
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};
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nvmem_firmware {
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compatible = "xlnx,zynqmp-nvmem-fw";
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#address-cells = <1>;
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#size-cells = <1>;
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soc_revision: soc_revision@0 {
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reg = <0x0 0x4>;
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};
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};
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pcap: pcap {
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compatible = "xlnx,zynqmp-pcap-fpga";
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};
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rst: reset-controller {
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compatible = "xlnx,zynqmp-reset";
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#reset-cells = <1>;
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};
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xlnx_dp_snd_card: dp_snd_card {
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compatible = "xlnx,dp-snd-card";
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status = "disabled";
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xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
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xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
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};
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xlnx_dp_snd_codec0: dp_snd_codec0 {
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compatible = "xlnx,dp-snd-codec";
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status = "disabled";
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clock-names = "aud_clk";
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};
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xlnx_dp_snd_pcm0: dp_snd_pcm0 {
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compatible = "xlnx,dp-snd-pcm";
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status = "disabled";
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dmas = <&xlnx_dpdma 4>;
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dma-names = "tx";
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};
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xlnx_dp_snd_pcm1: dp_snd_pcm1 {
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compatible = "xlnx,dp-snd-pcm";
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status = "disabled";
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dmas = <&xlnx_dpdma 5>;
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dma-names = "tx";
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};
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xilinx_drm: xilinx_drm {
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compatible = "xlnx,drm";
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status = "disabled";
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xlnx,encoder-slave = <&xlnx_dp>;
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xlnx,connector-type = "DisplayPort";
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xlnx,dp-sub = <&xlnx_dp_sub>;
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planes {
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xlnx,pixel-format = "rgb565";
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plane0 {
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dmas = <&xlnx_dpdma 3>;
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dma-names = "dma0";
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};
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plane1 {
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dmas = <&xlnx_dpdma 0>,
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<&xlnx_dpdma 1>,
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<&xlnx_dpdma 2>;
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dma-names = "dma0", "dma1", "dma2";
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};
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};
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};
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amba_apu: amba-apu@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0 0xffffffff>;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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reg = <0x0 0xf9010000 0x10000>,
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<0x0 0xf9020000 0x20000>,
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<0x0 0xf9040000 0x20000>,
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<0x0 0xf9060000 0x20000>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <1 9 0xf04>;
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};
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};
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amba: amba {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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can0: can@ff060000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clock-names = "can_clk", "pclk";
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reg = <0x0 0xff060000 0x0 0x1000>;
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interrupts = <0 23 4>;
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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power-domains = <&zynqmp_firmware PD_CAN_0>;
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};
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can1: can@ff070000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clock-names = "can_clk", "pclk";
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reg = <0x0 0xff070000 0x0 0x1000>;
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interrupts = <0 24 4>;
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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power-domains = <&zynqmp_firmware PD_CAN_1>;
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};
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cci: cci@fd6e0000 {
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compatible = "arm,cci-400";
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reg = <0x0 0xfd6e0000 0x0 0x9000>;
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ranges = <0x0 0x0 0xfd6e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1";
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reg = <0x9000 0x5000>;
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interrupt-parent = <&gic>;
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interrupts = <0 123 4>,
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<0 123 4>,
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<0 123 4>,
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<0 123 4>,
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<0 123 4>;
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};
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};
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/* GDMA */
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fpd_dma_chan1: dma@fd500000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd500000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 124 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14e8>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan2: dma@fd510000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd510000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 125 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14e9>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan3: dma@fd520000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd520000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 126 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14ea>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan4: dma@fd530000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd530000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 127 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14eb>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan5: dma@fd540000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd540000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 128 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14ec>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan6: dma@fd550000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd550000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 129 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14ed>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan7: dma@fd560000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd560000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 130 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14ee>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan8: dma@fd570000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd570000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 131 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x14ef>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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gpu: gpu@fd4b0000 {
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status = "disabled";
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compatible = "arm,mali-400", "arm,mali-utgard";
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reg = <0x0 0xfd4b0000 0x0 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
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interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
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clock-names = "gpu", "gpu_pp0", "gpu_pp1";
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power-domains = <&zynqmp_firmware PD_GPU>;
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};
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/* LPDDMA default allows only secured access. inorder to enable
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* These dma channels, Users should ensure that these dma
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* Channels are allowed for non secure access.
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*/
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lpd_dma_chan1: dma@ffa80000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xffa80000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 77 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x868>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan2: dma@ffa90000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xffa90000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 78 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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#stream-id-cells = <1>;
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iommus = <&smmu 0x869>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan3: dma@ffaa0000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xffaa0000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 79 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x86a>;
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan4: dma@ffab0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffab0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 80 4>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
xlnx,bus-width = <64>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x86b>;
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan5: dma@ffac0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffac0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 81 4>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
xlnx,bus-width = <64>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x86c>;
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan6: dma@ffad0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffad0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 82 4>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
xlnx,bus-width = <64>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x86d>;
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan7: dma@ffae0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffae0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 83 4>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
xlnx,bus-width = <64>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x86e>;
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan8: dma@ffaf0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffaf0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 84 4>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
xlnx,bus-width = <64>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x86f>;
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
mc: memory-controller@fd070000 {
|
|
compatible = "xlnx,zynqmp-ddrc-2.40a";
|
|
reg = <0x0 0xfd070000 0x0 0x30000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 112 4>;
|
|
};
|
|
|
|
nand0: nand@ff100000 {
|
|
compatible = "arasan,nfc-v3p10";
|
|
status = "disabled";
|
|
reg = <0x0 0xff100000 0x0 0x1000>;
|
|
clock-names = "clk_sys", "clk_flash";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 14 4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x872>;
|
|
power-domains = <&zynqmp_firmware PD_NAND>;
|
|
};
|
|
|
|
gem0: ethernet@ff0b0000 {
|
|
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 57 4>, <0 57 4>;
|
|
reg = <0x0 0xff0b0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x874>;
|
|
power-domains = <&zynqmp_firmware PD_ETH_0>;
|
|
};
|
|
|
|
gem1: ethernet@ff0c0000 {
|
|
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 59 4>, <0 59 4>;
|
|
reg = <0x0 0xff0c0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x875>;
|
|
power-domains = <&zynqmp_firmware PD_ETH_1>;
|
|
};
|
|
|
|
gem2: ethernet@ff0d0000 {
|
|
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 61 4>, <0 61 4>;
|
|
reg = <0x0 0xff0d0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x876>;
|
|
power-domains = <&zynqmp_firmware PD_ETH_2>;
|
|
};
|
|
|
|
gem3: ethernet@ff0e0000 {
|
|
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 63 4>, <0 63 4>;
|
|
reg = <0x0 0xff0e0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x877>;
|
|
power-domains = <&zynqmp_firmware PD_ETH_3>;
|
|
};
|
|
|
|
gpio: gpio@ff0a0000 {
|
|
compatible = "xlnx,zynqmp-gpio-1.0";
|
|
status = "disabled";
|
|
#gpio-cells = <0x2>;
|
|
gpio-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 16 4>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x0 0xff0a0000 0x0 0x1000>;
|
|
power-domains = <&zynqmp_firmware PD_GPIO>;
|
|
};
|
|
|
|
i2c0: i2c@ff020000 {
|
|
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 17 4>;
|
|
reg = <0x0 0xff020000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_I2C_0>;
|
|
};
|
|
|
|
i2c1: i2c@ff030000 {
|
|
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 18 4>;
|
|
reg = <0x0 0xff030000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_I2C_1>;
|
|
};
|
|
|
|
ocm: memory-controller@ff960000 {
|
|
compatible = "xlnx,zynqmp-ocmc-1.0";
|
|
reg = <0x0 0xff960000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 10 4>;
|
|
};
|
|
|
|
pcie: pcie@fd0e0000 {
|
|
compatible = "xlnx,nwl-pcie-2.11";
|
|
status = "disabled";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
msi-controller;
|
|
device_type = "pci";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 118 4>,
|
|
<0 117 4>,
|
|
<0 116 4>,
|
|
<0 115 4>, /* MSI_1 [63...32] */
|
|
<0 114 4>; /* MSI_0 [31...0] */
|
|
interrupt-names = "misc", "dummy", "intx",
|
|
"msi1", "msi0";
|
|
msi-parent = <&pcie>;
|
|
reg = <0x0 0xfd0e0000 0x0 0x1000>,
|
|
<0x0 0xfd480000 0x0 0x1000>,
|
|
<0x80 0x00000000 0x0 0x1000000>;
|
|
reg-names = "breg", "pcireg", "cfg";
|
|
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
|
|
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
|
|
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
|
|
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
|
|
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
|
|
power-domains = <&zynqmp_firmware PD_PCIE>;
|
|
pcie_intc: legacy-interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
|
|
qspi: spi@ff0f0000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "xlnx,zynqmp-qspi-1.0";
|
|
status = "disabled";
|
|
clock-names = "ref_clk", "pclk";
|
|
interrupts = <0 15 4>;
|
|
interrupt-parent = <&gic>;
|
|
num-cs = <1>;
|
|
reg = <0x0 0xff0f0000 0x0 0x1000>,
|
|
<0x0 0xc0000000 0x0 0x8000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x873>;
|
|
power-domains = <&zynqmp_firmware PD_QSPI>;
|
|
};
|
|
|
|
rtc: rtc@ffa60000 {
|
|
compatible = "xlnx,zynqmp-rtc";
|
|
status = "disabled";
|
|
reg = <0x0 0xffa60000 0x0 0x100>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 26 4>, <0 27 4>;
|
|
interrupt-names = "alarm", "sec";
|
|
calibration = <0x8000>;
|
|
};
|
|
|
|
serdes: zynqmp_phy@fd400000 {
|
|
compatible = "xlnx,zynqmp-psgtr";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd400000 0x0 0x40000>,
|
|
<0x0 0xfd3d0000 0x0 0x1000>,
|
|
<0x0 0xff5e0000 0x0 0x1000>;
|
|
reg-names = "serdes", "siou", "lpd";
|
|
nvmem-cells = <&soc_revision>;
|
|
nvmem-cell-names = "soc_revision";
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
|
|
<&zynqmp_reset ZYNQMP_RESET_DP>,
|
|
<&zynqmp_reset ZYNQMP_RESET_GEM0>,
|
|
<&zynqmp_reset ZYNQMP_RESET_GEM1>,
|
|
<&zynqmp_reset ZYNQMP_RESET_GEM2>,
|
|
<&zynqmp_reset ZYNQMP_RESET_GEM3>;
|
|
reset-names = "sata_rst", "usb0_crst", "usb1_crst",
|
|
"usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
|
|
"usb1_apbrst", "dp_rst", "gem0_rst",
|
|
"gem1_rst", "gem2_rst", "gem3_rst";
|
|
lane0: lane0 {
|
|
#phy-cells = <4>;
|
|
};
|
|
lane1: lane1 {
|
|
#phy-cells = <4>;
|
|
};
|
|
lane2: lane2 {
|
|
#phy-cells = <4>;
|
|
};
|
|
lane3: lane3 {
|
|
#phy-cells = <4>;
|
|
};
|
|
};
|
|
|
|
sata: ahci@fd0c0000 {
|
|
compatible = "ceva,ahci-1v84";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd0c0000 0x0 0x2000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 133 4>;
|
|
power-domains = <&zynqmp_firmware PD_SATA>;
|
|
#stream-id-cells = <4>;
|
|
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
|
|
<&smmu 0x4c2>, <&smmu 0x4c3>;
|
|
/* dma-coherent; */
|
|
};
|
|
|
|
sdhci0: mmc@ff160000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 48 4>;
|
|
reg = <0x0 0xff160000 0x0 0x1000>;
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
xlnx,device_id = <0>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x870>;
|
|
power-domains = <&zynqmp_firmware PD_SD_0>;
|
|
nvmem-cells = <&soc_revision>;
|
|
nvmem-cell-names = "soc_revision";
|
|
};
|
|
|
|
sdhci1: mmc@ff170000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 49 4>;
|
|
reg = <0x0 0xff170000 0x0 0x1000>;
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
xlnx,device_id = <1>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x871>;
|
|
power-domains = <&zynqmp_firmware PD_SD_1>;
|
|
nvmem-cells = <&soc_revision>;
|
|
nvmem-cell-names = "soc_revision";
|
|
};
|
|
|
|
pinctrl0: pinctrl@ff180000 {
|
|
compatible = "xlnx,pinctrl-zynqmp";
|
|
status = "disabled";
|
|
reg = <0x0 0xff180000 0x0 0x1000>;
|
|
};
|
|
|
|
smmu: smmu@fd800000 {
|
|
compatible = "arm,mmu-500";
|
|
reg = <0x0 0xfd800000 0x0 0x20000>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
#global-interrupts = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 155 4>,
|
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
|
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
|
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
|
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
|
|
};
|
|
|
|
spi0: spi@ff040000 {
|
|
compatible = "cdns,spi-r1p6";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 19 4>;
|
|
reg = <0x0 0xff040000 0x0 0x1000>;
|
|
clock-names = "ref_clk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_SPI_0>;
|
|
};
|
|
|
|
spi1: spi@ff050000 {
|
|
compatible = "cdns,spi-r1p6";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 20 4>;
|
|
reg = <0x0 0xff050000 0x0 0x1000>;
|
|
clock-names = "ref_clk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_SPI_1>;
|
|
};
|
|
|
|
ttc0: timer@ff110000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
|
reg = <0x0 0xff110000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_0>;
|
|
};
|
|
|
|
ttc1: timer@ff120000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
|
|
reg = <0x0 0xff120000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_1>;
|
|
};
|
|
|
|
ttc2: timer@ff130000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
|
|
reg = <0x0 0xff130000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_2>;
|
|
};
|
|
|
|
ttc3: timer@ff140000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
|
|
reg = <0x0 0xff140000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_3>;
|
|
};
|
|
|
|
uart0: serial@ff000000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 21 4>;
|
|
reg = <0x0 0xff000000 0x0 0x1000>;
|
|
clock-names = "uart_clk", "pclk";
|
|
power-domains = <&zynqmp_firmware PD_UART_0>;
|
|
};
|
|
|
|
uart1: serial@ff010000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 22 4>;
|
|
reg = <0x0 0xff010000 0x0 0x1000>;
|
|
clock-names = "uart_clk", "pclk";
|
|
power-domains = <&zynqmp_firmware PD_UART_1>;
|
|
};
|
|
|
|
usb0: usb0@ff9d0000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dwc3";
|
|
reg = <0x0 0xff9d0000 0x0 0x100>;
|
|
clock-names = "bus_clk", "ref_clk";
|
|
power-domains = <&zynqmp_firmware PD_USB_0>;
|
|
ranges;
|
|
nvmem-cells = <&soc_revision>;
|
|
nvmem-cell-names = "soc_revision";
|
|
|
|
dwc3_0: dwc3@fe200000 {
|
|
compatible = "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x0 0xfe200000 0x0 0x40000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 65 4>, <0 69 4>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x860>;
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,refclk_fladj;
|
|
/* dma-coherent; */
|
|
};
|
|
};
|
|
|
|
usb1: usb1@ff9e0000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dwc3";
|
|
reg = <0x0 0xff9e0000 0x0 0x100>;
|
|
clock-names = "bus_clk", "ref_clk";
|
|
power-domains = <&zynqmp_firmware PD_USB_1>;
|
|
ranges;
|
|
nvmem-cells = <&soc_revision>;
|
|
nvmem-cell-names = "soc_revision";
|
|
|
|
dwc3_1: dwc3@fe300000 {
|
|
compatible = "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x0 0xfe300000 0x0 0x40000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 70 4>, <0 74 4>;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu 0x861>;
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,refclk_fladj;
|
|
/* dma-coherent; */
|
|
};
|
|
};
|
|
|
|
watchdog0: watchdog@fd4d0000 {
|
|
compatible = "cdns,wdt-r1p2";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 113 1>;
|
|
reg = <0x0 0xfd4d0000 0x0 0x1000>;
|
|
timeout-sec = <60>;
|
|
reset-on-timeout;
|
|
};
|
|
|
|
lpd_watchdog: watchdog@ff150000 {
|
|
compatible = "cdns,wdt-r1p2";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 52 1>;
|
|
reg = <0x0 0xff150000 0x0 0x1000>;
|
|
timeout-sec = <10>;
|
|
};
|
|
|
|
xilinx_ams: ams@ffa50000 {
|
|
compatible = "xlnx,zynqmp-ams";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 56 4>;
|
|
interrupt-names = "ams-irq";
|
|
reg = <0x0 0xffa50000 0x0 0x800>;
|
|
reg-names = "ams-base";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
#io-channel-cells = <1>;
|
|
ranges;
|
|
|
|
ams_ps: ams_ps@ffa50800 {
|
|
compatible = "xlnx,zynqmp-ams-ps";
|
|
status = "disabled";
|
|
reg = <0x0 0xffa50800 0x0 0x400>;
|
|
};
|
|
|
|
ams_pl: ams_pl@ffa50c00 {
|
|
compatible = "xlnx,zynqmp-ams-pl";
|
|
status = "disabled";
|
|
reg = <0x0 0xffa50c00 0x0 0x400>;
|
|
};
|
|
};
|
|
|
|
xlnx_dp: dp@fd4a0000 {
|
|
compatible = "xlnx,v-dp";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd4a0000 0x0 0x1000>;
|
|
interrupts = <0 119 4>;
|
|
interrupt-parent = <&gic>;
|
|
clock-names = "aclk", "aud_clk";
|
|
xlnx,dp-version = "v1.2";
|
|
xlnx,max-lanes = <2>;
|
|
xlnx,max-link-rate = <540000>;
|
|
xlnx,max-bpc = <16>;
|
|
xlnx,enable-ycrcb;
|
|
xlnx,colormetry = "rgb";
|
|
xlnx,bpc = <8>;
|
|
xlnx,audio-chan = <2>;
|
|
xlnx,dp-sub = <&xlnx_dp_sub>;
|
|
xlnx,max-pclock-frequency = <300000>;
|
|
};
|
|
|
|
xlnx_dp_sub: dp_sub@fd4aa000 {
|
|
compatible = "xlnx,dp-sub";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd4aa000 0x0 0x1000>,
|
|
<0x0 0xfd4ab000 0x0 0x1000>,
|
|
<0x0 0xfd4ac000 0x0 0x1000>;
|
|
reg-names = "blend", "av_buf", "aud";
|
|
xlnx,output-fmt = "rgb";
|
|
xlnx,vid-fmt = "yuyv";
|
|
xlnx,gfx-fmt = "rgb565";
|
|
};
|
|
|
|
xlnx_dpdma: dma@fd4c0000 {
|
|
compatible = "xlnx,dpdma";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd4c0000 0x0 0x1000>;
|
|
interrupts = <0 122 4>;
|
|
interrupt-parent = <&gic>;
|
|
clock-names = "axi_clk";
|
|
power-domains = <&zynqmp_firmware PD_DP>;
|
|
dma-channels = <6>;
|
|
#dma-cells = <1>;
|
|
dma-video0channel {
|
|
compatible = "xlnx,video0";
|
|
};
|
|
dma-video1channel {
|
|
compatible = "xlnx,video1";
|
|
};
|
|
dma-video2channel {
|
|
compatible = "xlnx,video2";
|
|
};
|
|
dma-graphicschannel {
|
|
compatible = "xlnx,graphics";
|
|
};
|
|
dma-audio0channel {
|
|
compatible = "xlnx,audio0";
|
|
};
|
|
dma-audio1channel {
|
|
compatible = "xlnx,audio1";
|
|
};
|
|
};
|
|
};
|
|
};
|