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5818198e6a
Commit5bb2c550b1("arm: mvebu: Move internal registers in arch_very_early_init() function") moved code from file cpu.c to lowlevel.c, which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE. But the steps describing how to do it correctly were documented only in older U-Boot versions and commitcefd764222("arm: mvebu: Fix internal register config on A38x") probably unintentionally removed important details about MMU from code comments around. Commit5bb2c550b1("arm: mvebu: Move internal registers in arch_very_early_init() function") implemented code movement according to (now incomplete) comments which resulted in semi-broken code. The result is that I-cache is currently disabled for all Armada 38x boards and maybe there are some other (unreported / undetected) issues. Reimplement it correctly. First flush all caches, then disable MMU and L2 cache and then move Marvell internal registers. There is no need to explicitly disable I-cache. After this change lzmadec command with lzma image of 0x7000000 bytes is doing decompression just 5 seconds. Before this change it was 30 seconds. To make lowlevel.S code more readable, extend asm/pl310.h header file to be compatible with assembler and use macros from this file. Fixes:5bb2c550b1("arm: mvebu: Move internal registers in arch_very_early_init() function") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
55 lines
1.5 KiB
ArmAsm
55 lines
1.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/system.h>
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#include <asm/pl310.h>
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ENTRY(arch_very_early_init)
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#ifdef CONFIG_ARMADA_38X
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/*
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* Only with disabled MMU its possible to switch the base
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* register address on Armada 38x. Without this the SDRAM
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* located at >= 0x4000.0000 is also not accessible, as its
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* still locked to cache.
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*
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* So to fully release / unlock this area from cache, we need
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* to first flush all caches, then disable the MMU and
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* disable the L2 cache.
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*/
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/* Invalidate L1 I/D */
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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/* Disable MMU */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, #CR_M
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Disable L2 cache
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*
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* NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
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* but CONFIG_SYS_PL310_BASE is already calculated from base
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* address SOC_REGS_PHY_BASE.
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*/
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ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
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ldr r0, [r1, #L2X0_CTRL_OFF]
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bic r0, #L2X0_CTRL_EN
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str r0, [r1, #L2X0_CTRL_OFF]
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#endif
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/* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */
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ldr r0, =SOC_REGS_PHY_BASE
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ldr r1, =INTREG_BASE_ADDR_REG
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str r0, [r1]
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add r0, r0, #0xC000
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mcr p15, 4, r0, c15, c0
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bx lr
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ENDPROC(arch_very_early_init)
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